Senior Staff Verification Engineer (f/m/div)

Infineon Technologies; Bristol; On-site; GBP 60,000 - 80,000; Full time

Job summary

Infineon Technologies is seeking a Senior Staff Verification Engineer in Bristol to lead the development of IP verification environments. You will leverage your 8+ years of experience in Verification Engineering and expertise in System Verilog - UVM to enhance IP test bench architecture. Responsibilities include creating functional coverage models, debugging failing test cases, and collaborating with design teams. The role calls for a Bachelor's degree in Electrical/Electronic Engineering and fluency in English.

Qualifications

• 8+ years of experience in Verification Engineering.
• Strong understanding of verification concepts and System Verilog fundamentals.
• Eagerness to learn industry-standard verification methodologies like UVM.

Responsibilities

• Drive development and optimization of IP verification environments.
• Take ownership of complex IP verification with System Verilog - UVM.
• Ensure test benches meet sign-off targets and functional safety requirements.

Skills

System Verilog - UVM

Debugging workflows

Problem-solving

Teamwork

Time management

Education

Bachelor’s degree in Electrical/Electronic Engineering or related field

Job description

Overview

#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Senior Staff Verification Engineer on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Are you in?

Responsibilities

You will drive the development and optimization of IP verification environments, ensuring robust and efficient test bench architecture.

• Take full ownership of complex IP verification, developing System Verilog - UVM test bench environments
• Create functional coverage models and write constrained random tests for thorough validation
• Ensure test benches meet sign-off targets, including coverage and functional safety requirements
• Debug failing test cases and collaborate in design and concept meetings to resolve issues
• Drive verification strategy and enhance IP test bench architecture for future projects

Qualifications

• Bachelor’s degree in Electrical/Electronic Engineering or a related field
• 8+ years of experience in Verification Engineering, with hands‑on exposure to System Verilog - UVM (academic, internship, or professional experience)
• Strong understanding of verification concepts and System Verilog design and testbench fundamentals
• Eagerness to learn and apply industry-standard verification methodologies like UVM
• Understanding of debugging workflows and willingness to learn tools for test issue analysis
• Strong problem‑solving skills, effective teamwork, and solid time management
• Fluency in English

Additional Information

Please send us your CV in English.

Contact: Ana Rita Costa, LinkedIn

We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant’s experience and skills.

We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting.