Physical ASIC Design Implementation Engineer

TN United Kingdom; Cambridge; On-site; GBP 60,000 - 100,000; Full time

Job summary

Join a premier research center in nanotechnology as a Physical ASIC Design Implementation Engineer. This role involves leading low power design and detailed timing driven placement for advanced nodes. You will work closely with customers and the Physical Design team, ensuring successful project delivery from prototype to production. With a focus on professional development and competitive salary, this innovative firm values your contributions and supports your growth in a dynamic international environment. If you're passionate about advanced electronics and eager to make an impact, this is the opportunity for you.

Benefits

Visa sponsorship for relocation

Professional development programs

Competitive salary

Fringe benefits

Qualifications

• 10+ years of experience in physical implementation for advanced nodes (12 – 7nm).
• Expertise in power reduction techniques and hierarchical designs.

Responsibilities

• Lead low power design setup and detailed timing driven placement.
• Collaborate with Physical Design team for signoff closure.

Skills

Physical ASIC Design

Cadence Innovus Place & Route

Low Power Design (CPF)

Timing Driven Placement

Clock Tree Synthesis

Sign-off Timing (TEMPUS)

Physical Verification (DRC, ERC, LVS, ANT)

Hierarchical Design Partitioning

Education

Master Degree in Electronics

Tools

Cadence Innovus

TEMPUS

VOLTUS

Job description

Physical ASIC Design Implementation Engineer, Cambridge

Client: imec

Location: Cambridge, United Kingdom

Job Category: -

EU work permit required: Yes

Job Reference:

c89468180c24

Job Views:

5

Posted:

05.05.2025

Expiry Date:

19.06.2025

Job Description:

Physical ASIC Design Implementation Engineer

Engineering - Leuven | Just now

We are seeking a highly motivated Physical ASIC Design Implementation Engineer with a full understanding of the complete Cadence Innovus Place&Route flow.

What you will do

imec has been offering ASIC prototyping and production services for over 25 years, helping customers design and bring their chips from prototype to production. As part of the physical digital implementation group (Back-End), you will be in direct contact with customers for future projects, supporting layout, prototype, fabrication, and testing of advanced electronics.

Your responsibilities include:

1. Setting up low power design (CPF)
2. Floorplanning & power grid design
3. Detailed Timing Driven Placement
4. STA & design optimization for setup
5. Clock Tree Synthesis
6. Scan chain re-stitching
7. Detailed Timing Driven Route (incl. SI)
8. IPO’s (in-place optimization) for timing accuracy
9. Solving setup & hold violations
10. Sign-off extraction (SPEF)
11. Sign-off timing (TEMPUS)
12. Sign-off Power analysis (VOLTUS)
13. Physical verification (DRC, ERC, LVS, ANT)
14. Logic equivalent check

You will lead hierarchical design partitioning and work closely with the Physical Design team to drive signoff closure for tape-out. You will also serve as the technical liaison to customers regarding specifications.

What we do for you

Join a premier research center in nanotechnology at our offices in Cambridge, UK, Leuven, Belgium, or Eindhoven, Netherlands. We sponsor visas for relocation and support your professional development through our corporate university, investing in your technical and personal growth. We offer a competitive salary with fringe benefits, recognizing your valuable contributions.

Who you are

• You hold a Master Degree in Electronics
• You have at least 10 years of experience in physical implementation for advanced nodes (12 – 7nm) and hierarchical designs
• You are experienced in power reduction techniques such as gated clocks, voltage domains, memory retention, and switch-off power domains
• You possess excellent communication skills in English and can work within an international team
• You enjoy interacting with customers

Who we are

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