Senior DFT Architect for AI Accelerator SoC

NIF; West of England; Híbrido; GBP 100.000 - 165.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Private Medical

Dental and Vision

Contributory Pension

25 Days holiday plus bank holidays

Life/Critical Illness Insurance

Descripción de la vacante

Fractile is seeking a Senior / Principal DFT Engineer to own and evolve the DFT architecture for a leading AI accelerator SoC. You will set strategy, signoff criteria and drive the integration of DFT flows within the silicon development workflow.

Collaboration with RTL, physical design and test teams will be essential to enable robust, high-yield production testing. You will lead memory test strategies, at-speed testing, and power-aware approaches while mentoring a team of DFT engineers.

Formación

• 8+ years of experience in DFT for complex ASIC/SoC designs.
• Proven ownership of DFT architecture on at least one large tapeout.
• Deep expertise in scan, compression, ATPG and MBIST.
• Experience with industry tools (Synopsys or Tessent).

Responsabilidades

• Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan).
• Set DFT strategy, methodology, flow and signoff criteria.
• Drive integration of DFT tools and flows into the overall EDA environment.
• Define hierarchical DFT approach for multi-core designs and large memory systems.
• Define scan architecture, compression strategy, and ATPG approach.
• Define memory test and repair strategy for large embedded RAM.
• Establish power-aware and at-speed test strategies.
• Collaborate with RTL and physical design to ensure clean DFT integration and timing closure.
• Work with test and product engineering teams to bring up ATPG patterns on ATE and support production test.
• Mentor and guide DFT engineers.

Conocimientos

DFT for ASIC/SoC

ATPG/MBIST/scan

Synopsys Tessent

Clocking & power domains

Herramientas

Synopsys/Tessent

Descripción del empleo

Fractile is seeking a Senior / Principal DFT Engineer to own and evolve the DFT architecture for a leading AI accelerator SoC. You will set strategy, signoff criteria and drive the integration of DFT flows within the silicon development workflow.

Collaboration with RTL, physical design and test teams will be essential to enable robust, high-yield production testing. You will lead memory test strategies, at-speed testing, and power-aware approaches while mentoring a team of DFT engineers.