Senior Physical Design Engineer – AI Accelerator SoC Equity

Platform Recruitment; West of England; On-site; GBP 230,000 - 260,000; Full time

Benefits offered by this job

Equity

Competitive package

Job summary

Platform Recruitment is seeking a Senior or Staff Physical Design Engineer for a rapidly growing semiconductor company developing next-generation accelerator technology for high-performance AI computing in the UK. You will own physical design from architecture to sign-off, collaborating with analogue, digital and DFT engineers to deliver cutting-edge mixed-signal solutions.

Responsibilities include floorplanning, placement, routing, timing closure, clock distribution, power-grid design, and DFT

Qualifications

• Architect and implement high-performance digital control solutions.
• Floorplanning, placement, routing and timing closure.
• Develop low-power, low-skew clock networks.
• Design power grids around complex analogue floorplans.
• Timing analysis across analogue and digital interfaces.
• DRC, LVS and ERC closure on advanced nodes.
• Python and Tcl for EDA flow automation.
• Experience with sub-7nm tape-outs, PCIe/SerDes is a plus.

Responsibilities

• Architecting and implementing high-performance digital control solutions.
• Floorplanning, placement, routing and timing closure.
• Developing low-power, low-skew clock-distribution networks.
• Designing power grids around complex analogue floorplans.
• Performing timing analysis across analogue and digital interfaces.
• Achieving DRC, LVS and ERC closure on advanced-node processes.
• Customising and automating physical-design flows using Python and Tcl.
• Supporting DFT implementation and successful tape-out.

Skills

Digital design

Floorplanning

Place & route

CTS/STA

Python scripting

Tcl scripting

PD flow automation

Tools

Python scripting

Tcl scripting

Job description

Platform Recruitment is seeking a Senior or Staff Physical Design Engineer for a rapidly growing semiconductor company developing next-generation accelerator technology for high-performance AI computing in the UK. You will own physical design from architecture to sign-off, collaborating with analogue, digital and DFT engineers to deliver cutting-edge mixed-signal solutions.

Responsibilities include floorplanning, placement, routing, timing closure, clock distribution, power-grid design, and DFT