Lead DFT Architect — Chip-Level Test Strategy

Aion Silicon; Greater London; Hybrid; GBP 70,000 - 90,000; Full time

Job summary

Aion Silicon is seeking an experienced DFT Engineer to lead chip-level Design for Test execution. The role involves ensuring high-quality DFT implementation and technical leadership within teams. Candidates should have a relevant degree and over 10 years of DFT engineering experience. Expertise with Siemens or Synopsys DFT tools and strong project management skills are crucial. This position offers flexibility to work from various global locations, including the UK.

Qualifications

• Typically 10+ years of experience in Design for Test (DFT) engineering.
• Strong experience in ATPG and test coverage improvements.
• Demonstrated capability to lead DFT design projects.

Responsibilities

• Lead DFT strategy definition and implementation.
• Provide industry-leading technical guidance in DFT.
• Contribute to technical thought leadership.

Skills

Design for Test expertise

Problem solving

Project management

DFT tools knowledge (Siemens/Synopsys)

Teamwork

Education

Degree/Masters or PhD in relevant subject

Tools

DFT tools from Siemens

DFT tools from Synopsys

Job description

Aion Silicon is seeking an experienced DFT Engineer to lead chip-level Design for Test execution. The role involves ensuring high-quality DFT implementation and technical leadership within teams. Candidates should have a relevant degree and over 10 years of DFT engineering experience. Expertise with Siemens or Synopsys DFT tools and strong project management skills are crucial. This position offers flexibility to work from various global locations, including the UK.