DFT Engineer: Next-Gen ASIC Test Architect

IC Resources; Cambridge; On-site; GBP 70,000 - 110,000; Full time

Job summary

IC Resources is growing its ASIC team in Cambridge, delivering next‑generation silicon. The DFT Engineer will define and implement DFT across SoC/IP, integrating scan, MBIST, EDT, SSN and IJTAG while collaborating with design, verification and physical teams to ensure testability and high yields.

You will work across architecture to production, balancing test coverage, implementation complexity and time‑to‑market, with mentoring duties for fellow engineers and a focus on robust, scalable DFT

Qualifications

• Experience working within modern ASIC or SoC development flows.
• Familiarity with IJTAG / IEEE 1687 and related test access standards.
• Knowledge of advanced silicon technologies and manufacturing fault models.
• Experience supporting vector translation and production bring-up on ATE platforms.
• Previous experience mentoring or coaching other engineers.

Responsibilities

• Define DFT strategies at chip, subsystem and IP level.
• Implement structural and functional DFT methodologies across complex ASIC designs.
• Insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructure.
• Verify DFT implementation and debug related issues throughout the design cycle.
• Support implementation and sign-off, including timing constraints, timing closure, power analysis and formal equivalence checking.
• Work closely with Physical Design and Verification teams to ensure successful integration.
• Support ATPG generation, silicon bring-up and manufacturing test.
• Mentor and support other engineers within the team.

Skills

Siemens Tessent

ATPG

MBIST

Scan architecture

DFT verification

IJTAG

Tcl scripting

Python scripting

Clocking knowledge

Mentoring others

Tools

Siemens Tessent

Job description

IC Resources is growing its ASIC team in Cambridge, delivering next‑generation silicon. The DFT Engineer will define and implement DFT across SoC/IP, integrating scan, MBIST, EDT, SSN and IJTAG while collaborating with design, verification and physical teams to ensure testability and high yields.

You will work across architecture to production, balancing test coverage, implementation complexity and time‑to‑market, with mentoring duties for fellow engineers and a focus on robust, scalable DFT