EDA ENGINEER (CHIP DESIGN PROCESS FLOW)-AEROSPACE AND DEFENSE

Gentrian; London; On-site; GBP 60,000 - 80,000; Full time

Job summary

An innovative firm in the aerospace and defense sector is seeking an EDA Engineer to lead chip design processes. This role offers the opportunity to work on cutting-edge technologies and contribute to high-performance data handling solutions. You will be responsible for designing integrated circuits and ensuring efficient metadata management for high concurrency environments. With a focus on innovation and speed, this position promises a dynamic work environment where your expertise will drive advancements in technology. If you have a passion for engineering and a desire to make an impact in a vital industry, this is the perfect opportunity for you.

Qualifications

• 15+ years experience in EDA and CAD flow development.
• In-depth knowledge of chip design process and RTL coding.

Responsibilities

• Design and translate requirements through integrated circuits.
• Conduct hardware/software design, simulation, and verification.

Skills

Python

Shell

Perl

TCL

EDA (Electronic Design Automation)

CAD flow development

RTL coding

Education

Electronic Engineering Degree

Job description

EDA ENGINEER (CHIP DESIGN PROCESS FLOW) - AEROSPACE AND DEFENSE

Bullisher is a data-centric fintech solution provider in the aerospace and defense industry for institutional level investors, looking to disrupt and revolutionize a $3 trillion dollar industry. We spearhead an industry-leading Blackbox to facilitate and administer trade agreements pioneered by a vehicle, driven by our new generation benchmark delivering solutions through innovation with uncompromising agility.

JOB DESCRIPTION:

The oversight workloads require you to design and translate abstract requirements through integrated circuits for a de-ghosting application and concurrent application. It involves multiple stages, including hardware and software design, simulation or verification, physical and timing analyses, and tape-out. The driving factors for this are added functionality, a high level of integration, and advancing technology. Areas to cover will include RTL/Circuit design, simulation or verification followed by logic synthesis and then physical implementation checks followed by final tape-out. Usage will be growing exponentially due to smaller geometries and increasing functionality. Our overarching goal is to efficiently handle billions of small files with a very high metadata workload, enabling thousands of compute processes reading or writing data concurrently with high performance read, write, and delete capabilities. The storage architecture specification is designed from the ground-up for high concurrency and high performance environments, requiring exceptional metadata handling and performance for both small and large files.

PHYSICAL DEMANDS: This position requires the ability to communicate and exchange information and utilize equipment necessary to perform the job.

ENVIRONMENT: This position will operate in the following areas of the organization: [ROCKET FUEL] MISSION INTELLIGENCE DIVISION. Innovation, powering speed and space exploration in science systems.

Employees must be legally authorized to work in the UK. Verification of employment eligibility will be required at the time of hire. Visa sponsorship is not available for this position.

QUALIFICATIONS, KEY REQUIREMENTS AND SKILLS SET:

• Must have an Electronic Engineering Degree.
• Proven expertise in programming languages such as Python, Shell, Perl, and TCL.
• Preferably a semiconductor industry background.
• Member of a professional designated body (e.g. IET, InstMC).
• 15+ years proven experience in EDA (Electronic Design Automation) flow development and CAD flow development.
• In-depth knowledge of the chip design process.
• Proficient in RTL coding experience.

INTERVIEW PROCESS:

• STAGE 1: COGNITIVE ABILITY TEST
• STAGE 2: COGNITIVE ASSESSMENT SCREENING: WITH A 30+ YEARS EXPERIENCE PSYCHOLOGIST
• STAGE 3: PRE-SCREENING (verification checks & DV security clearance)
• STAGE 4: INTERVIEW WITH THE CEO, CTO & CHIEF ENGINEER