Design Verification Engineer

JR United Kingdom; Newport; On-site; GBP 40,000 - 70,000; Full time

Job summary

A leading global Semiconductor company is seeking a Design Verification Engineer to join their team in Bristol. This role involves verifying complex digital designs through developing verification plans, maintaining test cases, and performing coverage analysis. Ideal candidates will have a strong background in UVM, SystemVerilog, and scripting languages.

Qualifications

• Solid understanding and hands-on experience with UVM and SystemVerilog.
• Mid-Senior level experience.
• Proficiency in scripting languages.

Responsibilities

• Develop and implement verification plans for digital designs using UVM.
• Write and maintain verification test benches, test cases, and coverage models.
• Debug test failures and collaborate with design teams.

Skills

UVM

SystemVerilog

Perl

Python

TCL

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering

Job description

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Design Verification Engineer, Newport, Wales

Client: IC Resources

Location: Newport, Wales, United Kingdom

Job Category: Other

EU work permit required: Yes

Job Views: 1

Posted: 31.05.2025

Expiry Date: 15.07.2025

Job Description:

This position is based in Bristol, UK.

I am looking for a skilled Design Verification Engineer to join a dynamic team at a global Semiconductor company in Bristol. The Design Verification Engineer will be responsible for verifying complex digital designs and ensuring that functionality and performance meet the required specifications.

Responsibilities

• Develop and implement verification plans for digital designs using UVM (Universal Verification Methodology).
• Collaborate with cross-functional teams to understand design requirements and contribute to the verification strategy.
• Write and maintain verification test benches, test cases, and coverage models.
• Perform functional and code coverage analysis to ensure comprehensive verification.
• Debug test failures and work closely with design teams to resolve issues.
• Contribute to the improvement of verification processes and methodologies.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Solid understanding and hands-on experience with UVM and SystemVerilog.
• Proficiency in scripting languages such as Perl, Python, or TCL.
• Mid-Senior level experience.

As a Design Verification Engineer, you will collaborate with design and verification teams to ensure successful verification and validation of digital designs. Your responsibilities include writing and maintaining test cases, analyzing code coverage, debugging, and contributing to process improvements. You will also engage in cross-functional communication to align on verification strategies.

For more information, please contact Rachel Mason at IC Resources.