Design Verification Engineer

JR United Kingdom; Stoke-on-Trent; On-site; GBP 45,000 - 70,000; Full time

Job summary

A leading technological company is seeking a Design Verification Engineer based in Stoke-on-Trent. The role involves verifying CPU connectivity, writing test plans, and executing verification tasks using advanced methodologies. Successful candidates will have experience with software development tools and techniques, ensuring high-quality design verification in a cutting-edge environment.

Qualifications

• Experience in CPU connectivity verification and developing test cases.
• Proficiency with verification methodologies like UVM.
• Ability to write test plans and debug failures.

Responsibilities

• Verify CPU connectivity to IP blocks.
• Develop test methodologies and test benches.
• Provide verification reports showing test results.

Skills

CPU connectivity

C code

Test plans

Debugging

Verification techniques

Tools

GNU toolchain

Verilog

SystemVerilog

UVM

Job description

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Design Verification Engineer, Stoke-on-Trent

Client: ALOIS Solutions

Location: Stoke-on-Trent, United Kingdom

Job Category: Other

EU work permit required: Yes

Job Views:

1

Posted:

31.05.2025

Expiry Date:

15.07.2025

Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)
• Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification, and close coverage for all the design blocks in the SoCs/Subsystems
• Run regressions, debug test failures, and file bug reports as needed
• Develop tests to meet functional and code coverage requirements based on analysis of coverage gaps
• Provide verification reports showing all tests passing on the RTL
• Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog-based testbenches, and C, SystemVerilog, UVM-based test cases