Design Verification Engineer

JR United Kingdom; London; On-site; GBP 50,000 - 90,000; Full time

Job summary

An established industry player is seeking a talented GPU Verification Engineer to join their innovative GPU Division. This role offers a unique opportunity to leverage your hardware verification skills on cutting-edge designs that drive graphics, AI, and connectivity processors. You will be responsible for all verification activities related to GPU components, from planning to sign-off, while also creating verification plans and developing UVM testbench components. Join a powerhouse where your contributions will directly impact the development of graphics and AI chips at the core of beloved electronic products. If you are passionate about technology and eager to make a difference, this is the perfect opportunity for you.

Qualifications

• Proven track record in developing verification environments for complex RTL designs.
• Excellent understanding of verification methodology and challenges.

Responsibilities

• Responsible for delivery of verification activities for GPU components.
• Create verification plans and develop UVM testbench components.

Skills

GPU Verification

Root-Cause Analysis

Constrained-Random Verification

SystemVerilog

UVM

Tools

UVM Testbench

Job description

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Work on cutting edge designs within a prestigious group!

I am seeking a GPU Verification Engineer to join my clients growing GPU Division. This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within their prestigious Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics, AI or connectivity processor and related IP.

You will get the chance to work for a powerhouse whereby you will spend your time creating the graphics and AI chips that are at the core of your favourite electronic products.

You will:

• Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off.
• Create verification plans, develop and maintain UVM testbench components.
• Participate in all stages of design specification definition providing feedback from the verification perspective.
• Develop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plans.
• Be responsible for the definition, effort estimation and tracking of your own work.
• Be able to influence and advance our GPU verification methodology.
• Have the opportunity to lead, coach and mentor other members of the team.
• Participate in design and verification reviews and recommend improvements.

Qualifications:

• Have a proven track record of developing verification environments for complex RTL designs.
• Have excellent understanding of constrained-random verification methodology and challenges of verification closure.
• Be confident in defining verification requirements, and work out the implementation approach and details of a testbench.
• Be able to do root-cause analysis of complex issues and resolve them in a timely manner.
• Have excellent knowledge of SystemVerilog and UVM.

For more information and a confidential discussion on this superb opportunity, contact Rachel Mason at IC Resources.