Design Verification Engineer

JR United Kingdom; Leeds; On-site; GBP 35,000 - 60,000; Full time

Job summary

A leading engineering firm seeking a Design Verification Engineer in Leeds, West Yorkshire. The role involves verifying CPU connectivity, developing test plans, and providing verification reports. The candidate should be proficient in UVM, Verilog, and testing methodologies.

Qualifications

• Experience with CPU connectivity and verification in SoCs.
• Proficient in writing test cases and developing test benches.
• Familiar with UVM and Verilog/System Verilog methodologies.

Responsibilities

• Verify CPU connectivity to IP blocks and write corresponding test plans.
• Run regressions and debug test failures, reporting bugs as necessary.
• Provide verification report summarizing the results of all tests conducted.

Skills

CPU connectivity verification

Test plan writing

Functional verification

Regression testing

Debugging

UVM usage

Verilog/System Verilog

Tools

GNU toolchain

Job description

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Design Verification Engineer, leeds, west yorkshire

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Client:

ALOIS Solutions

Location:

leeds, west yorkshire, United Kingdom

Job Category:

Other

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EU work permit required:

Yes

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Job Views:

5

Posted:

09.06.2025

Expiry Date:

24.07.2025

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Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)

• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems

• Run regressions, debug test failures and file bug report as needed.

• Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.

• Provide verification report as needed to show all implemented tests passing on the RTL.

• Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases