Design Verification Engineer

JR United Kingdom; Wakefield; On-site; GBP 40,000 - 60,000; Full time

Job summary

A leading semiconductor company in the UK is seeking a Verification Engineer to join their team. The role involves developing and executing comprehensive test plans for SoCs, utilizing advanced verification techniques such as UVM and System Verilog. The ideal candidate should be proficient in debugging, writing testcases, and ensuring all functional coverage is met. This position offers an opportunity to contribute to high-impact projects in a collaborative environment.

Qualifications

• Experience with UVM and verification methodologies in semiconductor design.
• Ability to write test plans and debug test failures.
• Strong knowledge in functional verification and test development.

Responsibilities

• Write and execute testcases for functional verification in SoCs.
• Develop and implement verification tests and methodologies.
• Provide reports on all implemented tests and their outcomes.

Skills

Debugging

Test plan development

Verification techniques

Functional coverage analysis

Tools

UVM

Verilog

System Verilog

C

GNU toolchain

Job description

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)

• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems

• Run regressions, debug test failures and file bug report as needed.

• Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.

• Provide verification report as needed to show all implemented tests passing on the RTL.

• Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases