Design Verification Engineer

JR United Kingdom; Warrington; On-site; GBP 40,000 - 60,000; Full time

Job summary

A leading technology firm is seeking a Design Verification Engineer in Warrington specializing in CPU connectivity and functional verification. The role involves writing test plans, debugging, and using advanced methodologies including UVM. Ideal candidates will have a strong background in Verilog/SystemVerilog and proven communication skills.

Qualifications

• Experience with CPU connectivity and test plan development.
• Proficient in Verilog/SystemVerilog, UVM, and debugging.
• Ability to run regressions and analyze coverage gaps.

Responsibilities

• Verify CPU connectivity to IP blocks using ASM boot and C code.
• Write test plans and develop tests for coverage requirements.
• Run regressions, debug test failures, and provide verification reports.

Skills

CPU connectivity

Test methodologies

Debugging

Functional verification

Verilog/SystemVerilog

UVM

Tools

ASM boot

GNU toolchain

Job description

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Design Verification Engineer, Warrington, Cheshire

Client: ALOIS Solutions

Location: Warrington, Cheshire

Job Category: Other

EU work permit required: Yes

Job Views: 5

Posted: 09.06.2025

Expiry Date: 24.07.2025

Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, C code, GNU toolchain)
• Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification, and close coverage for all design blocks in the SoCs/Subsystems.
• Run regressions, debug test failures, and file bug reports as needed.
• Develop tests to meet functional and code coverage requirements based on coverage gap analysis.
• Provide verification reports showing all tests passing on the RTL.
• Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, C, SystemVerilog, UVM test cases.