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Design Verification Engineer

JR United Kingdom

Sheffield

On-site

GBP 35,000 - 55,000

Full time

5 days ago
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Job summary

A leading company is seeking a Design Verification Engineer to work in Sheffield. The role involves verifying CPU connectivity, writing test plans, and debugging failures using various methodologies like UVM and System Verilog. This position provides an opportunity to be a part of innovative projects in a dynamic team environment.

Qualifications

  • Experience in design verification roles required.
  • Familiarity with CPU connectivity and test methodologies.
  • Proficient in writing testcases and debugging failures.

Responsibilities

  • Verify CPU connectivity to IP blocks using ASM boot and C code.
  • Write test plans, define methodologies, and develop test benches.
  • Run regressions, debug test failures, and file bug reports.

Skills

Verification
Debugging
Test Planning
C Code
UVM
Verilog/System Verilog

Tools

GNU Toolchain

Job description

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Design Verification Engineer, sheffield, south yorkshire

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Client:

ALOIS Solutions

Location:

sheffield, south yorkshire, United Kingdom

Job Category:

Other

-

EU work permit required:

Yes

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Job Views:

1

Posted:

31.05.2025

Expiry Date:

15.07.2025

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Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)

• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems

• Run regressions, debug test failures and file bug report as needed.

• Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.

• Provide verification report as needed to show all implemented tests passing on the RTL.

• Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases

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