Design Verification Engineer

Apple Inc.; Cambridge; On-site; GBP 50,000 - 75,000; Full time

Job summary

Join Apple's UK GPU design centre as a Design Verification Engineer, responsible for pre-silicon RTL verification of low power embedded graphics cores. Collaborate with engineers to ensure seamless verification flow, utilizing SystemVerilog, UVM, and C++ to achieve high-confidence testing coverage.

Qualifications

• Strong background in computer architecture, preferably in graphics.
• Solid foundation in verification methodology.

Responsibilities

• Verify complex GPU designs using SystemVerilog, UVM, and C++.
• Develop verification plans in coordination with design leads.
• Create and maintain verification test bench components.

Skills

SystemVerilog

UVM

C++

Computer Architecture

Verification Methodology

Job description

Add to Favourites: Design Verification Engineer

Do your life’s best work here - with the whole world watching. Join a rapidly growing team at our UK GPU design centre. At Apple, new ideas and complex challenges quickly become phenomenal products, services, and customer experiences.

The Design Verification Engineer will be responsible for the pre-silicon RTL verification of blocks in low power embedded graphics cores. This includes a deep understanding of the micro-architectural details of their block and how it functions within the broader GPU design. A strong computer architecture background, preferably in graphics, and a solid foundation in verification methodology will be essential to achieve high-confidence testing coverage.

Description

• Use SystemVerilog, UVM, and C++ with industry-leading simulation tools and methodologies to verify complex GPU designs.
• Develop verification plans in coordination with design leads and architects.
• Create and maintain verification test bench components and environments.
• Generate directed and random tests.
• Run simulations and debug design and environment issues.
• Build functional coverage points, analyze coverage, and enhance test environments to target coverage gaps.
• Build automated verification flows for block verification.

Minimum Qualifications

[Details not provided]

Preferred Qualifications

• Collaborate with other block and core level engineers to ensure seamless verification flow.