Systems IP - Staff/Principal Verification Engineer

TN United Kingdom; Cambridge; On-site; GBP 60,000 - 85,000; Full time

Job summary

A leading company is seeking a Staff/Principal Verification Engineer to join their System IP team in Cambridge. The role involves developing verification methodologies for complex hardware IP, enhancing testbenches, and mentoring team members. Ideal candidates will have strong skills in SystemVerilog and UVM, along with experience in constrained-random verification.

Qualifications

• Experience with constrained-random verification and complex verification environments.
• Proficiency in SystemVerilog and UVM.
• Good scripting skills and ability to plan and estimate work.

Responsibilities

• Specify and develop hardware verification testbenches for new hardware IP.
• Enhance existing testbenches for better performance and quality.
• Mentor team members and collaborate with other engineering teams.

Skills

Constrained-random verification

SystemVerilog

UVM

Software engineering

Scripting skills

Job description

Systems IP - Staff/Principal Verification Engineer, Cambridge

Client: arm limited

Location: Cambridge, United Kingdom

Job Category: Other

EU work permit required: Yes

Job Reference: 11a90870e6f7

Job Views: 3

Posted: 19.05.2025

Expiry Date: 03.07.2025

Job Description:

The Role

This position offers an excellent opportunity for an experienced verification engineer to join the System IP team, working on hardware design and verification methodologies for complex IP at the core of Arm-based systems. The role focuses on the Interconnect product team, developing scalable, customizable IP for various applications.

Responsibilities:

• Specify and develop hardware verification testbenches for new hardware IP.
• Enhance existing testbenches for better performance and quality.
• Identify and implement process improvements in verification methodologies.
• Review design changes for verification complexity.
• Manage verification environments from investigation to closure.
• Script and optimize verification flows, analyze simulation data using data science techniques.
• Mentor team members and collaborate with other engineering teams to ensure high-quality IP.

Required Skills and Experience:

• Experience with constrained-random verification and complex verification environments.
• Proficiency in SystemVerilog and UVM.
• Software engineering skills, including object-oriented programming, data structures, and algorithms.
• Experience in developing testbenches and verification processes.
• Good scripting skills and ability to plan and estimate work.

'Nice To Have' Skills and Experience:

• Leadership and mentoring experience.
• Knowledge of multiprocessing microarchitecture, cache coherence, and bus protocols (AMBA5 CHI, AMBA4 ACE, AXI).
• Experience with Formal Verification testbenches.
• Strong communication skills and team collaboration.
• Problem-solving focus and dedication.

In return:

Contribute to technologies impacting millions of devices, develop your technical leadership, and grow as an expert within the team.