Computing Researcher (PAYE Contractor)

Huawei; Cambridge; On-site; GBP 55,000 - 75,000; Full time

Job summary

A leading technology company is seeking a Computing Hardware and Software Co-design Researcher in Cambridge. This role demands expertise in CPU/NPU architectures and a keen focus on performance workload modeling. Responsibilities include integrating hardware and software solutions and driving vertical integration for next-gen processors. Candidates must possess advanced degrees and strong analytical skills, as well as exceptional communication abilities with teams globally.

Qualifications

• Strong expertise in computer architecture, HPC, AI, and networking.
• Solid track record of scientific publications in leading conferences.
• Fluent in English; native Chinese speaker is a plus.

Responsibilities

• Plan and implement tool systems for architectural exploration and performance analysis.
• Drive software and hardware vertical integration and co-optimization features.
• Maintain strong technical insight and broad ICT knowledge.

Skills

Technical expertise in CPU/NPU architecture

Performance workload modeling

Analytical skills

Proficiency in programming languages

Co-design methodologies

Education

Master's or PhD in Computer Science, Electrical Engineering, or Computer Engineering

Job description

Overview

We are looking for a Computing Hardware and Software Co-design Researcher with expertise in CPU and NPU architectures and a focus on performance workload modeling. The ideal candidate will be a technical expert in the compute domain, responsible for integrating hardware and software solutions. This role also includes supporting the local research team in communicating effectively with the headquarter in China, ensuring seamless collaboration. Strong analytical skills, proficiency in relevant programming languages, and a passion for innovative co-design methodologies are essential.

Responsibilities

• Plan and implement tool systems for architectural exploration and performance analysis as a key member of a team at the forefront of CPU/NPU development.
• Drive software and hardware vertical integration and plan software/hardware co-optimization features for next-generation processors.
• Possess a strong understanding of CPU/NPU architecture and workload extraction, with a good grasp of compiler, binary analysis, and software/hardware co-optimization.
• Demonstrate a strong technical background with understanding of one or more of the following: memory, interconnect, cluster computing, HPC servers, AI servers, CPU/GPU/NPU/DPU accelerators, and hardware/software co-design.
• Leverage extensive industry experience in workload modeling and CPU/NPU architecture development.
• Quickly learn new areas through academic research, conferences, and discussions with experts.
• Maintain strong technical insight and broad ICT knowledge, with awareness of emerging technologies.

Qualifications

• Master's or PhD degree in Computer Science, Electrical Engineering, or Computer Engineering, with strong expertise in computer architecture, HPC, AI, and networking.
• Solid track record of scientific publications in leading conferences.
• Fluent in English (spoken and written); native Chinese speaker is a plus.