Senior ASIC Design Engineer – AI Accelerator / SoC

ECARX; Greater London; On-site; GBP 120,000 - 180,000; Full time

Job summary

Ecarx Co. is seeking an experienced Senior ASIC Design Engineer to contribute to architecture, microarchitecture, and RTL development for AI accelerators and high-performance SoCs.

You will translate specs into synthesizable RTL, optimize for PPA, and support the full ASIC lifecycle in a collaborative team. The role focuses on hands-on digital design, RTL implementation, debugging, and close collaboration with architecture, verification, and physical design teams to deliver production-quality

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• 5+ years hands-on experience in digital ASIC/SoC design, microarchitecture, and RTL implementation.
• Strong architecture/microarchitecture knowledge with hands-on design in GPU/NPU/complex SoC architectures.
• Proficient in Verilog/SystemVerilog RTL design and translating specs into microarchitecture.
• Experience with RTL simulation, synthesis, lint and timing analysis.

Responsibilities

• Develop detailed microarchitecture specifications based on system requirements.
• Design and implement complex digital logic using Verilog/SystemVerilog.
• Develop high-performance datapaths, control logic, FSMs, arbitration, and interfaces.
• Optimize RTL for timing, power, and area; perform RTL reviews and debugging.
• Collaborate with architecture/verification/physical design to deliver production-quality silicon.
• Design and implement functional blocks for AI accelerators, GPU, NPU, or SoC subsystems.
• Develop memory interfaces, DMA engines, and interconnect fabrics.
• Interface with IP and system integration teams to ensure correct interfaces.
• Support silicon bring-up, post-silicon validation, and hardware/software integration.
• Participate in ASIC development lifecycle from spec to tape-out and post-silicon steps.

Skills

ASIC/SoC design

Verilog/SystemVerilog

RTL debugging

Microarchitecture

GPU/NPU architectures

Education

Bachelor’s or Master’s in EE/CE/CS

Tools

Synthesis tools (e.g., Synopsys)

RTL linting tools

Job description

We are seeking an experienced and highly motivated Senior ASIC Design Engineer to contribute to the architecture, microarchitecture, and RTL development of next-generation AI accelerators and high-performance SoC subsystems.

The ideal candidate will have strong hands-on experience in digital ASIC design, with a solid understanding of GPU, NPU, or complex SoC subsystem architectures. The candidate should be proficient in translating functional specifications into detailed microarchitecture and synthesizable RTL, optimizing designs for performance, power, and area (PPA), and supporting the complete ASIC development lifecycle.

This position focuses on hands-on digital design, RTL implementation, functional debugging, and collaboration with architecture, verification, and physical design engineers to deliver production-quality silicon.

Key Responsibilities

1. ASIC Microarchitecture and RTL Design

• Develop detailed microarchitecture specifications based on system-level and functional requirements.
• Design and implement complex digital logic using Verilog/SystemVerilog.
• Develop high-performance datapaths, control logic, finite state machines, arbitration mechanisms, and communication interfaces.
• Implement efficient pipelining, buffering, flow control, and resource-sharing mechanisms.
• Optimize RTL designs for timing, power consumption, silicon area, and implementation feasibility.
• Perform RTL code reviews, design analysis, and functional debugging.
• Collaborate with architecture engineers to evaluate design trade-offs and improve subsystem performance.

2. AI Accelerator and SoC Subsystem Design

• Design and implement functional blocks and subsystems for AI accelerators, GPU, NPU, or complex SoC architectures.
• Develop compute pipelines, memory interfaces, DMA engines, on-chip interconnects, and data movement logic.
• Understand and implement hardware mechanisms supporting parallel computation, high-throughput processing, and efficient memory access.
• Optimize data movement, memory bandwidth utilization, latency, and overall subsystem performance.
• Collaborate with system architects and algorithm engineers to translate computational requirements into efficient hardware implementations.

3. Memory and High-Speed Interface Integration

• Design and integrate memory controllers, on-chip interconnects, and high-speed interface subsystems.
• Work with memory subsystem architectures, including memory arbitration, buffering, transaction ordering, and data flow control.
• Support integration of standard interfaces such as AMBA AXI and other SoC interconnect protocols.
• Collaborate with IP and system integration teams to ensure functional correctness and interface compatibility.
• Analyze interface performance, bandwidth utilization, and latency bottlenecks.

4. ASIC Development and Design Implementation

• Participate in the ASIC development lifecycle from specification and microarchitecture through RTL design, verification, synthesis, physical implementation, and tape-out.
• Develop synthesizable, maintainable, and production-quality RTL that meets design requirements.
• Perform lint checks, clock-domain crossing (CDC) analysis, and reset-domain crossing (RDC) analysis.
• Support logic synthesis, static timing analysis, and timing closure.
• Work with physical design engineers to address timing, congestion, power, and area challenges.
• Analyze and resolve functional and implementation issues identified during simulation, synthesis, and physical design.
• Support silicon bring-up, post-silicon debugging, and validation activities as needed.

5. Functional Verification and Hardware/Software Integration

• Collaborate with verification engineers to develop functional verification plans and test scenarios.
• Support IP-level and SoC-level verification, including simulation, debugging, and regression analysis.
• Analyze simulation failures and debug RTL functional issues using waveforms, logs, and assertions.
• Participate in hardware/software interface definition, including control/status registers, interrupts, and programming models.
• Support FPGA prototyping, emulation, and hardware/software integration testing.
• Work with firmware and software engineers to resolve system-level functional issues.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of hands-on experience in digital ASIC/SoC design, microarchitecture, and RTL implementation.
• Strong architecture and microarchitecture knowledge, with hands-on design experience in at least one of the following:
• GPU or parallel computing architectures
• NPU, AI accelerator, or machine learning processor architectures
• Complex SoC subsystems, such as memory controllers, interconnect fabrics, DMA engines, or high-performance processing subsystems
• Strong proficiency in Verilog/SystemVerilog RTL design.
• Experience translating functional specifications into microarchitecture specifications and synthesizable RTL.
• Solid understanding of digital logic design, pipelining, finite state machines, datapaths, memory systems, and on-chip interconnect architectures.
• Experience with RTL simulation, debugging, synthesis, lint, and static timing analysis.
• Familiarity with clock-domain crossing (CDC), reset design, and timing constraints.
• Experience working with verification engineers to debug functional issues and achieve design correctness.
• Understanding of ASIC design flow from specification through synthesis, physical implementation, and tape-out.
• Strong analytical, debugging, and problem-solving skills.
• Ability to independently design, implement, and debug complex ASIC functional blocks.

Preferred Qualifications

• Direct design experience with GPU, NPU, AI accelerator, or heterogeneous computing SoCs.
• Knowledge of chip-to-chip and die-to-die interconnect technologies, including UCIe (Universal Chiplet Interconnect Express) or other high-speed interconnect protocols.
• Knowledge of LPDDR memory technologies, particularly LPDDR5/LPDDR5X and LPDDR6, including memory controller architecture and interface integration.
• Knowledge of PCIe, particularly PCIe Gen5/Gen6, including controller architecture, transaction processing, and subsystem integration.
• Familiarity with NoC architectures, cache coherency, memory consistency, and high-bandwidth data movement.
• Experience with AMBA AXI/ACE/CHI or other industry-standard SoC interconnect protocols.
• Understanding of AI/ML workloads, including matrix multiplication, tensor operations, and inference acceleration.
• Experience with hardware/software co-design, firmware interfaces, or system-level integration.
• Familiarity with UVM-based functional verification, SystemVerilog Assertions (SVA), or formal verification.
• Experience with FPGA prototyping, hardware emulation, or post-silicon validation.
• Familiarity with low-power design techniques, including clock gating, power domains, and power optimization.
• Experience with advanced semiconductor process technologies, including 7nm, 5nm, 3nm, or below.
• Experience with ASIC designs that have successfully completed tape-out and silicon bring-up.