Senior Verification Engineer - SoC/ARM (Hybrid)

Arm Limited; Valbonne; Hybrid; EUR 65,000 - 90,000; Full time

Job summary

Arm is seeking a Senior Verification Engineer to verify RTL features for upcoming ARM SoC projects. You will collaborate with the RTL team to understand microarchitecture and develop advanced verification environments, including stimulus generators and checkers, ensuring new features align with architectural requirements.

You will verify functionality while protecting existing capabilities, implement verification strategies, and contribute to evolving verification methodologies.

Qualifications

• Requires minimum 3 years of proven IP/SOC verification experience.
• Advanced proficiency in SystemVerilog and Verilog with deep knowledge of UVM methodology.
• Solid understanding of SoC verification using C test cases.
• Experience writing verification plans and test plans.
• Experience with Testbench development using standard verification methodologies.
• Experience with ARM-based designs and/or ARM System Architectures.
• Exposure to scripting languages (Perl/Python).
• Strong interpersonal skills for cross-functional, distributed teams.

Responsibilities

• Collaborate with RTL team to understand microarchitecture details.
• Develop and enhance verification environments, stimulus generators, and checkers.
• Verify new features function as specified without impacting existing functionality.
• Implement verification strategies with other verification engineers.
• Contribute to continual improvements in verification methodology.
• Mentor early-tenure verification engineers.

Skills

SystemVerilog

Verilog

UVM

C Testcases

Testbench

ARM-based designs

Perl

Python

Collaboration

Education

Bachelor's or Master’s in Computer Science or Electrical/Computer Engineering

Tools

Perl

Python

Job description

Arm is seeking a Senior Verification Engineer to verify RTL features for upcoming ARM SoC projects. You will collaborate with the RTL team to understand microarchitecture and develop advanced verification environments, including stimulus generators and checkers, ensuring new features align with architectural requirements.

You will verify functionality while protecting existing capabilities, implement verification strategies, and contribute to evolving verification methodologies.