Senior Process Integration Engineer

Intellectual Capital Resources Ltd; Île-de-France; On-site; EUR 90,000 - 130,000; Full time

Job summary

Intellectual Capital Resources Ltd. is seeking a Senior Process Integration Engineer to lead end-to-end product integration from front-end wafer fabrication to final test, including cryogenic reliability assessments.

You will interface with manufacturing partners to ensure robust process flows, high yield, and reliable performance across cross-functional teams. The role requires 8+ years in semiconductor or MEMS process integration, experience with multi-layer fabrication, and strong data

Qualifications

• Master's or PhD in materials science, physics, microelectronics or related discipline.
• 8+ years of hands-on semiconductor or MEMS process integration experience with ownership of product yield.
• Strong knowledge of multi-layer fabrication processes including lithography, thin-film deposition, plating, etching, lift-off, CMP and polymer dielectrics.

Responsibilities

• Own and optimise front-end semiconductor or MEMS process flows with external foundries to ensure process quality.
• Manage end-to-end product integration from wafer fabrication through thinning, dicing, assembly and final test.
• Develop yield models, analyse wafer maps and defects, set quality targets and drive improvements with partners.
• Correlate process, inspection, assembly, electrical and cryogenic test data to identify failure mechanisms and implement corrective actions.
• Collaborate with back-end assembly teams on bumping, flip-chip and bonding to ensure manufacturability and reliability.

Skills

English fluency

Communication skills

Statistical yield modelling

Wafer-level analysis

Statistical process control

Education

Master's or PhD in materials science, physics, microelectronics or related discipline

Tools

Python

JMP

DOE

FMEA

Job description

Our innovative deep-tech client is currently searching for a Senior Process Integration Engineer to lead end-to-end product integration, from front-end wafer fabrication at external foundries through assembly, testing and cryogenic reliability. The role will act as the technical interface with manufacturing partners, ensuring robust process flows, high yield and reliable product performance. Working closely with process development, design and test teams, the successful candidate will connect front-end manufacturing with back-end assembly and final product qualification.

Key responsibilities are as follows:

• Process integration: Own and optimise front-end semiconductor or MEMS process flows, working closely with external foundries to ensure process quality and consistency.
• End-to-end product integration: Manage the integrated manufacturing flow from wafer fabrication through thinning, dicing, assembly and final test.
• Yield optimisation: Develop yield models, analyse wafer maps and defects, establish quality targets, and drive improvements with manufacturing partners.
• Data analysis and root-cause investigation: Correlate process, inspection, assembly, electrical and cryogenic test data to identify failure mechanisms and implement corrective actions.
• Back-end process alignment: Collaborate with assembly specialists on bumping, flip-chip and bonding to ensure front-end processes support manufacturability and reliability.
• Reliability and qualification: Lead risk assessments, failure analysis, design of experiments and product qualification, including cryogenic testing where applicable.
• Cross-functional engineering: Work with design, RF, mechanical and test teams to ensure manufacturing processes meet electrical, thermal and mechanical requirements.
• Supplier and knowledge management: Lead technical reviews, manage process changes and deviations, and maintain internal documentation of manufacturing knowledge.

Essential requirements are as follows:

• At least eight years of hands-on semiconductor or MEMS process integration experience, including ownership of product yield.
• Strong knowledge of multi-layer fabrication processes, including lithography, thin-film deposition, plating, etching, lift-off, CMP and polymer dielectrics.
• Experience with statistical yield modelling, wafer-level analysis, statistical process control and cross-stage data correlation, using tools such as Python or JMP.
• Working knowledge of back-end processes, including bumping, flip-chip assembly, bonding, wafer thinning and dicing.
• Experience managing external foundries or manufacturing partners, including process reviews, change control and yield improvement.
• Practical experience with FMEA, DOE, structured root-cause analysis and product qualification.
• Comfortable working hands-on in cleanroom environments and travelling regularly to manufacturing partners.
• Strong communication skills and professional fluency in English.
• Master's degree or PhD in materials science, physics, microelectronics or a related discipline.