Senior Integration & Yield Engineer — Superconducting Quantum Circuits H/F

Entangled Future; Aubervilliers; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

BSPCE plan

IP bonuses

Flexible remote policy up to 40% a měs

Parental plan with crèche support

25 days vacation + RTT

Transportation cost coverage

Competitive health coverage

Job summary

Alice & Bob in Aubervilliers is seeking a Senior Integration & Yield Engineer to join the Foundries & Process Integration team. You will ensure that device designs translate into high-performing fabricated circuits and own yield monitoring across fabrication flows, providing data-driven support for process improvements.

Responsibilities include leading root-cause analysis, performing advanced statistical analyses, and developing robust integration and DFM guidelines to scale qubit production

Qualifications

• Master’s degree or Ph.D. in Physics, Materials Science, or related field.
• 3+ years hands-on experience in semiconductor or superconducting circuit nanofabrication or process integration.
• Proven expertise in yield engineering, SPC, DOE, and statistical analysis tools.
• Proficiency in Python scripting to connect design and fabrication workflows.
• Strong problem-solving mindset and root-cause analysis methodologies (5 Whys, FMEA, Ishikawa).

Responsibilities

• Own yield monitoring across fabrication flows: define metrics, build automated dashboards, and provide real-time visibility of fab performance and yield.
• Lead root cause analysis of systematic and random yield detractors, in collaboration with the chip manufacturing teams.
• Perform advanced statistical analysis (using Python/JMP) to ensure process stability and control variability.
• Develop strategies to reduce inductance/frequency non-uniformity within and across wafers, improving qubit performance.
• Define and maintain robust integration flows of POR, ensuring design-to-fab alignment.
• Establish Design for Manufacturability guidelines and maintain reference fabrication flows and KPIs.
• Own LUTs linking design parameters to Josephson junction fabrication and maintain accuracy as processes evolve.
• Translate device designs into fabrication-ready wafer layouts and build Python-based tools to automate the design-to-wafer pipeline.

Skills

Statistical analysis

Root-cause analysis

Cross-disciplinary collaboration

Problem solving

Education

Master's degree or Ph.D. in Physics/Materials Science

Tools

Python

JMP

Job description

Senior Integration & Yield Engineer — Superconducting Quantum Circuits H/F at Alice & Bob, Aubervilliers. A senior-level full time position in the Foundries and Process Integration team, listed under hardware engineering.

We’re a diverse team of 250+ brilliant minds from over 35 countries united by a single goal: to revolutionise computing with a practical fault‑tolerant quantum machine. Are you ready to take on unprecedented challenges and contribute to revolutionising technology? Join us, and let’s shape the future of quantum computing together!

About the role

We are seeking a Senior Integration & Yield Engineer to join the Foundries & Process Integration team within the Quantum Hardware & Infrastructure department.

The role sits at the interface between qubit design and the chip manufacturing teams. Its purpose is twofold: ensure that device designs translate reliably into high‑performing fabricated circuits, and provide the data foundation for process improvement decisions. You will own yield monitoring across our fabrication flows, lead the analysis of fabrication and test data, and maintain the interfaces between design and manufacturing — supporting the scale‑up from tens of qubits to a few hundred, and enabling our path toward fault‑tolerant quantum computing.

Recruitment Process

• Screening Call with Alexandra, Talent Acquisition Specialist (30 min)
• Hiring Manager Interview with Alireza (45 min)
• Technical Interview/Presentation with the Team (120 min)
• Leadership Team Interview (45 min)
• Fit Interview (45 min)
• Reference check

- Our success is your success: own it with our BSPCE plan

- Direct IP Compensation: Earn substantial bonuses for driving the core patents that define our quantum architecture.

- Flexible remote policy, up to 40 % a month

- A P arental plan including additional benefits such as crèche support or additional days‑off to take care of under 12 years old children

- 25-day vacation policy (as per French law) + RTT

- Half of transportation cost coverage (as per French law), or yearly allowance for the die‑hard bicycle users

- Competitive health coverage, with Alan.

Responsibilities

• Own yield monitoring across fabrication flows: define metrics, build automated dashboards (wafer reports), and provide real‑time visibility of fab performance and yield.
• Lead root cause analysis of systematic and random yield detractors, in collaboration with the chip manufacturing teams.
• Perform advanced statistical analysis (using Python/JMP) to ensure process stability and control variability.
• Develop strategies to reduce inductance/frequency non‑uniformity within and across wafers, improving the consistency of qubit performance (frequency targeting, coherence times).
• Define and maintain robust integration flows of POR (process of reference), ensuring design‑to‑fab alignment.
• Establish Design for Manufacturability (DFM) guidelines.
• Document and maintain reference fabrication flows, yield dashboards, and process KPIs to support process reviews.
• Own the look‑up tables (LUT) linking design parameters to Josephson junction fabrication, and maintain their accuracy as fabrication processes evolve.
• Test and implement Design Rule Manual (DRM) extensions in collaboration with the design and fabrication teams, and establish Design for Manufacturability (DFM) guidelines.
• Translate device designs into fabrication‑ready wafer layouts (wafer layout generation), and develop Python‑based tools to automate the design‑to‑wafer pipeline and reduce manual handoff errors.

Requirements

• Master’s degree or Ph.D. in Physics, Materials Science, or a related field.
• 3+ years of hands‑on experience in semiconductor or superconducting circuit nanofabrication or process integration.
• Proven expertise in yield engineering, SPC, DOE, and statistical analysis tools.
• Proficiency in Python scripting to adapt and extend tools connecting design and fabrication workflows.
• Strong problem‑solving mindset and command of root cause analysis methodologies (5 Whys, FMEA, Ishikawa).
• Excellent communication skills and the ability to work effectively in a cross‑disciplinary environment.
• Experience in the fabrication or characterization of superconducting circuits, or in cryogenic testing is a plus.