Secure Processor Verification via Clock Glitch Modeling

CEA; Grenoble; Sur place; EUR 36 000 - 45 000; Plein temps

Résumé du poste

CEA-List (Grenoble) invites applications for a 12-month postdoctoral position focused on formal modeling of clock glitch attacks for security verification of processors. The project will bridge physical fault injection experiments with formal verification to evaluate hardware/software countermeasures on RISC-V CV32E40S and OpenTitan Ibex.

Applicants should hold a PhD in computer science, electrical engineering, or embedded systems and have experience in hardware security, fault injection, formal

Qualifications

• PhD in related field required.
• Experience in hardware security and fault injection is desirable.

Responsabilités

• Formally model clock glitch effects based on experiments and ETFM.
• Validate fault models experimentally using TRAITOR and µArchiFI.
• Analyze protected processors (e.g., RISC-V CV32E40S, OpenTitan Ibex) and assess countermeasures.

Connaissances

Hardware security

Fault injection

Formal verification

RTL design

RISC-V

Embedded software

Processor architectures

Formation

PhD in computer science/engineering

Description du poste

CEA-List (Grenoble) invites applications for a 12-month postdoctoral position focused on formal modeling of clock glitch attacks for security verification of processors. The project will bridge physical fault injection experiments with formal verification to evaluate hardware/software countermeasures on RISC-V CV32E40S and OpenTitan Ibex.

Applicants should hold a PhD in computer science, electrical engineering, or embedded systems and have experience in hardware security, fault injection, formal