Next-Gen CPU Verification Intern (FPGA & C++)

Arm Limited

Valbonne

Teletrabalho

EUR 23 000 - 31 000

Tempo integral

Há 3 dias
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Currículo e carta de apresentação personalizados, prontos a enviar.

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Resumo da oferta

Arm Limited invites motivated Masters students to join as Verification Intern at its Sophia Antipolis design centre for a 5-6 month program commencing in 2027. You will join the CPU verification team, helping verify Arm Cortex IPs with tools and languages like UVM, SystemVerilog, C, C++, and Python.

You will develop testbenches and scripts, tackling varied topics from AI-assisted verification to CI framework resilience, under experienced engineers’ guidance.

Qualificações

  • Master’s degree in Electronics, Computer Engineering, or CS (BAC+5) and current enrollment for a 5- or 6-month internship.
  • Experience with at least one programming language such as C, C++, Python.
  • Strong problem-solving skills and attention to detail.

Responsabilidades

  • Support verification of Arm Cortex IPs using methods from constrained random simulation to FPGA.
  • Develop testbenches, scripts, and models in languages such as UVM, SystemVerilog, C, C++, Python.
  • Collaborate with engineers to learn and contribute across product development.
  • Work on real projects from day one with guidance and dedicated personal development time.
  • Contribute to internship topics including AI in verification and CI framework resilience.

Conhecimentos

C/C++
Python
Problem solving
CPU curiosity
Teamwork

Formação académica

Master's degree BAC+5 in Electronics/CS

Ferramentas

UVM
SystemVerilog
C
C++

Descrição da oferta de emprego

Arm Limited invites motivated Masters students to join as Verification Intern at its Sophia Antipolis design centre for a 5-6 month program commencing in 2027. You will join the CPU verification team, helping verify Arm Cortex IPs with tools and languages like UVM, SystemVerilog, C, C++, and Python.

You will develop testbenches and scripts, tackling varied topics from AI-assisted verification to CI framework resilience, under experienced engineers’ guidance.

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