Internship: Pre-Silicon Fault Modeling for Security (Grenoble)

CEA; Grenoble; On-site; EUR 12,000 - 16,000; Full time

Job summary

The French Alternative Energies and Atomic Energy Commission (CEA) invites motivated students for an internship in Grenoble to develop experimentally grounded fault models for pre‑silicon security verification. You will bridge RTL‑level fault analysis with layout information and contribute to refining fault models for real‑world attacks.

Working within the LFIM group, you will access state‑of‑the‑art equipment and collaborate with top researchers in hardware security, potentially culminating in

Qualifications

• Experience with VHDL/Verilog and RTL design methods.
• Familiarity with RISC‑V and security evaluation methodologies.
• Knowledge of fault injection, formal verification, or security analysis.
• Excellent written and oral communication in English.

Responsibilities

• Develop methods to correlate experimental observations with RTL/netlist structures.
• Extend μArchiFI framework to support experimentally grounded fault models.
• Gain hands‑on experience in hardware security and fault injection campaigns.
• Collaborate with leading research teams in hardware design and security.

Skills

VHDL/Verilog

RTL design

RISC-V architectures

English communication

Education

Master’s program (M2) or engineering school

Job description

The French Alternative Energies and Atomic Energy Commission (CEA) invites motivated students for an internship in Grenoble to develop experimentally grounded fault models for pre‑silicon security verification. You will bridge RTL‑level fault analysis with layout information and contribute to refining fault models for real‑world attacks.

Working within the LFIM group, you will access state‑of‑the‑art equipment and collaborate with top researchers in hardware security, potentially culminating in