Internship - Experimentally Grounded Fault Modeling for Pre-Silicon Security Verification-Grenoble-H/F

CEA; Grenoble; On-site; EUR 12,000 - 16,000; Full time

Job summary

The French Alternative Energies and Atomic Energy Commission (CEA) invites motivated students for an internship in Grenoble to develop experimentally grounded fault models for pre‑silicon security verification. You will bridge RTL‑level fault analysis with layout information and contribute to refining fault models for real‑world attacks.

Working within the LFIM group, you will access state‑of‑the‑art equipment and collaborate with top researchers in hardware security, potentially culminating in

Qualifications

• Experience with VHDL/Verilog and RTL design methods.
• Familiarity with RISC‑V and security evaluation methodologies.
• Knowledge of fault injection, formal verification, or security analysis.
• Excellent written and oral communication in English.

Responsibilities

• Develop methods to correlate experimental observations with RTL/netlist structures.
• Extend μArchiFI framework to support experimentally grounded fault models.
• Gain hands‑on experience in hardware security and fault injection campaigns.
• Collaborate with leading research teams in hardware design and security.

Skills

VHDL/Verilog

RTL design

RISC-V architectures

English communication

Education

Master’s program (M2) or engineering school

Job description

Internship - Experimentally Grounded Fault Modeling for Pre-Silicon Security Verification-Grenoble-H/F

Category

Information system

Contract

Internship

Job title

Internship - Experimentally Grounded Fault Modeling for Pre-Silicon Security Verification-Grenoble-H/F

Subject

Opportunities

• Develop methods to correlate experimental observations with RTL/netlist structures and physical layout information.
• Extend the μArchiFI framework to support experimentally grounded fault models for pre-silicon verification.
• Develop a first-hand experience in hardware security and the exploitation of fault injection attacks, based on real-world laser injection campaigns.
• Collaborate with leading research teams in hardware design and hardware security.

As an intern at the CEA, you will have the opportunity to work within a world-renowned research environment. Our teams consist of passionate and dedicated experts, providing an ideal setting for learning and collaboration. You will have access to state-of-the-art equipment and top-tier research resources to carry out your assignments. The work conducted may potentially lead to a scientific publication.

Context :

Laser fault injection (LFI) attacks pose a significant threat to security-critical embedded systems, enabling adversaries to manipulate processor behavior by inducing transient or permanent faults in integrated circuits. While post-silicon evaluations on fabricated devices provide concrete evidence of vulnerabilities, they are often costly, time‑consuming, and difficult to interpret precisely. Conversely, pre-silicon security verification (e.g. using tools like μArchiFI [https://github.com/CEA-LIST/uArchiFI]) allows for systematic exploration of fault scenarios at the RTL or netlist levels but relies on abstract fault models that may not accurately reflect real-world physical attacks. This disconnect creates a methodological gap: experimental campaigns reveal actual fault effects [2], but their implications for design‑time security assurance (e.g. wether a fault injection leads to a concrete vulnerability exploitation) needs further exploration [3].

The emergence of open‑source hardware architectures, such as RISC‑V‑based processors, offers new opportunities to bridge this gap. When RTL descriptions, synthesized netlists, and physical layout information are available, it becomes possible to correlate experimental observations with microarchitectural behavior. Existing fabricated test chips, already available in the lab in advanced technologies [4] (e.g., 22nm FD‑SOI or 28nm CMOS), further enable the validation of fault models under realistic conditions. However, existing approaches lack a systematic methodology to translate experimental data into physically grounded fault models that can be effectively used in pre-silicon verification.

What do we expect from you?

The long-term objective is to develop a bottom‑up methodology for deriving and validating pre-silicon fault models from laser fault injection campaigns. This internship will focus on bridging the gap between RTL‑level fault analysis, enriched with layout‑level information, and results of fault injection campaigns. This work may lead to the design of new fault models derived from experimental observations and physical design information. By integrating these refined models into tools like μArchiFI, the internship will contribute to improving the accuracy and traceability of pre-silicon security assessments, ultimately supporting the development of more robust processors.

#Cea-List

Methods / Means

https://github.com/CEA-LIST/uArchiFI

We are seeking a highly motivated student in the final year of a master’s program (M2) or engineering school, with a strong background in computer engineering, digital design, or hardware security. The ideal candidate should have:

• Experience with VHDL/Verilog, RTL design, and hardware description languages.
• Familiarity with microprocessor architectures (e.g., RISC‑V) and security evaluation methodologies is a plus.
• Knowledge of fault injection, formal verification, or security analysis. Strong analytical and problem‑solving skills, with the ability to work independently and in a team.
• Excellent written and oral communication skills in English.

A passion for hardware security research and an interest in pursuing a PhD in this field would be highly valued. The internship offers the possibility of continuing toward a doctoral thesis, focusing on advancing the methodology for experimentally grounded fault modeling and its application to real‑world security challenges.

Site

Grenoble

Job location

Location

Grenoble

Prepared diploma

Recommended training

master’s program (M2) or engineering school

PhD opportunity

Oui

Requester

01/02/2027

General information

Organisation

The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :

• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.

Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners.

The CEA is established in ten centers spread throughout France.

Reference

2026-42332

The Laboratory for Innovative Functions for Mixed‑Signal Circuits (LFIM) is tasked with the study and design of digital and mixed‑signal electronic circuits that meet requirements for energy efficiency, compact size, real‑time operation, and operational reliability. These circuits are applied in a wide range of systems and fields, such as high-performance computing architectures and low-power embedded systems—areas that now converge in the context of quantum computing, where a cryogenic environment imposes conflicting demands regarding performance and power dissipation.

The technologies developed within the laboratory leverage the latest advancements in nanoelectronics. The LFIM studies, designs, and integrates digital and mixed‑signal processing architectures onto silicon to address application needs in areas including high-performance computing, the Internet of Things (IoT), radio-frequency (RF) circuits, and cyber‑physical systems.