Remote Quantum Chip Layout Architect

Alice & Bob; Paris; Hybride; EUR 90 000 - 140 000; Plein temps

Avantages offerts par ce poste

BSPCE plan

Direct IP compensation bonuses

Remote policy up to 40% monthly

Parental plan with crèche support

Urban Sports Club

Moka.care mental health support

25-day vacation + RTT

Transport cost coverage

Résumé du poste

Alice & Bob in Paris, France seeks a seasoned physical-design engineer to build the layout infrastructure for a scalable quantum computer. The role focuses on PDK, layout compilers, parasitic extraction, and hierarchical verification, applied to superconducting hardware rather than quantum physics.

You will drive automation toward multi-qubit scale, develop tile-based methods, and ensure robust signoff before mask release, reflecting the company’s bold quantum vision.

Qualifications

• 5+ years in physical design, custom/analog layout, PDK development, or mask data prep in a semiconductor context (CMOS backend, RF/analog, MEMS, or photonics).
• Track record scaling a layout methodology with generators, PCells, or hierarchical flows on larger designs.

Responsabilités

• Build and own the PDK — layer stack, technology file, parametric cells — and their DRC/LVS decks.
• Design a tile-based, hierarchical layout methodology with standardized tiles and programmatic instantiation.
• Write and maintain layout generators (Python/GDS or vendor scripting) that produce DRC-clean GDSII/OASIS with minimal manual drawing.
• Drive automation targets toward 50%+ automated layout at 400 qubits, 80%+ at 1,000, 90%+ at 10,000+.
• Keep DRC/LVS/PEX runtime and file size tractable via hierarchical verification.
• Evaluate and deploy the EDA toolchain and integrate with EM-simulation handoff.
• Sign off at design review gates before mask release.

Connaissances

Layout automation

English proficiency

Communication

Outils

Calibre xRC/xACT

GDSII/OASIS

Python gdstk / Layout API

Description du poste

Alice & Bob in Paris, France seeks a seasoned physical-design engineer to build the layout infrastructure for a scalable quantum computer. The role focuses on PDK, layout compilers, parasitic extraction, and hierarchical verification, applied to superconducting hardware rather than quantum physics.

You will drive automation toward multi-qubit scale, develop tile-based methods, and ensure robust signoff before mask release, reflecting the company’s bold quantum vision.