Postdoc: FeFET Ternary Computing - Circuit to System

CENTRALE LYON; Écully; Sur place; EUR 42 000 - 48 000; Plein temps

Résumé du poste

CENTRALE LYON in Écully invites a Post-Doctoral researcher to advance ferroelectric-based ternary computing, from circuit design to system integration. The position is on-site for 12 months, with funding from ANR HiLoDaNets and DFG, starting January 2027.

The project focuses on FeFET-based ternary IMC, design libraries, architecture modeling, and co-design strategies for CNNs and DSP workloads, aiming for energy efficiency and close collaboration with international partners.

Qualifications

• PhD in microelectronics, computer architecture, or related field.
• Hands-on experience with industrial EDA tools (Cadence Virtuoso/Spectre, Synopsys).
• Knowledge of non-volatile memory devices (FeFET/FeCap, RRAM, PCM).
• Experience with architecture-level simulation and hardware/software co-design.
• Proficiency in HDL and scripting languages (Python, Shell).
• Fluent scientific English; French welcome.

Responsabilités

• Design standard cell library based on FeFET devices for synthesis flow.
• Design and optimize ternary arithmetic units (MACs, adders, comparators).
• Develop and refine system-level models of FeFET-based IMC units.
• Investigate hardware/software co-design strategies for CNNs and DSP workloads.
• Assess energy, performance, and accuracy trade-offs vs. binary IMC references.
• Contribute to design methodology for ternary ferroelectric circuits.

Connaissances

Circuit and architecture design

Emerging memory technologies

System-level design & simulation

HDL programming

Python scripting

RISC-V knowledge

Formation

PhD in microelectronics/computer architecture

Outils

Cadence Virtuoso/Spectre

Synopsys EDA tools

Description du poste

CENTRALE LYON in Écully invites a Post-Doctoral researcher to advance ferroelectric-based ternary computing, from circuit design to system integration. The position is on-site for 12 months, with funding from ANR HiLoDaNets and DFG, starting January 2027.

The project focuses on FeFET-based ternary IMC, design libraries, architecture modeling, and co-design strategies for CNNs and DSP workloads, aiming for energy efficiency and close collaboration with international partners.