HFT & Ultra-Low Latency Intern (DPU/SmartNICs)

Kalray; Montbonnot-Saint-Martin; Hybrid; EUR 8,900 - 13,000; Full time

Benefits offered by this job

Hybrid work

Meal vouchers

Team building and other activities

Job summary

Kalray offers a final-year internship in the DPU Services team focusing on ultra-low-latency networking for financial markets. You will prototype measurement setups, explore kernel-bypass stacks, and evaluate DPU/SmartNIC solutions on real hardware to minimize tick-to-trade latency.

Working in a small, agile team, you’ll gain hands-on experience with DPUs, NFV concepts, and hardware timestamping, contributing to benchmarks and architecture recommendations in a hybrid, collaborative environment.

Qualifications

• C networking: Ethernet, IP, UDP unicast/multicast, TCP, L2/L3 switching; PTP and VXLAN knowledge a plus.
• Development: Modern C and/or C++ on Linux, Python for automation/measurement analysis, Git.
• Systems: Server architecture, Linux kernel mechanisms (interrupts, scheduling, core isolation).
• Hardware timestamping and PTP knowledge.
• Nanosecond‑level latency measurement experience.
• DPU SDKs (NVIDIA DOCA) and network architecture for trading platforms.

Responsibilities

• Benchmark ultra-low-latency solutions: kernel-bypass stacks and hardware cards; reference methodologies.
• Develop an event-to-trade measurement prototype with market data feed and latency measurement.
• Benchmark commercially available solutions evaluating latency, throughput and CPU usage.
• Evaluate integration of SDN and firewall offloads on DPU/SmartNIC architectures.
• Present benchmark report, architectural recommendations and potential open-source contributions.

Skills

C/C++ programming

Python scripting

Linux

Networking

PTP & VXLAN knowledge

DPU SDKs (NVIDIA DOCA)

Performance measurement

Agile / teamwork

Education

Engineering student (3rd year)

Tools

DPDK

eBPF/XDP

NVIDIA DOCA

Job description

Kalray offers a final-year internship in the DPU Services team focusing on ultra-low-latency networking for financial markets. You will prototype measurement setups, explore kernel-bypass stacks, and evaluate DPU/SmartNIC solutions on real hardware to minimize tick-to-trade latency.

Working in a small, agile team, you’ll gain hands-on experience with DPUs, NFV concepts, and hardware timestamping, contributing to benchmarks and architecture recommendations in a hybrid, collaborative environment.