Digital IP Design Intern for AI/DPU Hardware

Kalray; Montbonnot-Saint-Martin; Hybrid; EUR 10,000 - 17,000; Full time

Benefits offered by this job

Hybrid work

Meal vouchers

Team building activities

Laser tag

Escape games

Sailing

Skiing

Go-karting

Karaoke

Job summary

Kalray is offering an internship in Montbonnot (France) with the hardware digital design team. You will contribute to the development of DSP IPs and DPUs for AI and HPC data centers, from microarchitecture to physical synthesis, on a cutting-edge 4nm process.

You will work on RTL design (SystemVerilog/Verilog/VHDL), timing analysis, and integration into networking subsystems, gaining hands-on experience across the full design cycle in an agile, collaborative environment.

Qualifications

• Hardware description language experience: SystemVerilog/Verilog/VHDL.
• Familiarity with logic synthesis and static timing analysis; EDA tools a plus.
• Scripting: Python, Tcl, Shell; C/C++ is a plus; interest in networks and protocols.

Responsibilities

• Analyze requirements and specifications for the IP.
• Define microarchitecture including pipelines, data paths, and memories.
• Write IP microarchitecture specifications and RTL design.
• Support unit verification and timing analysis of the IP.
• Perform synthesis and physical implementation study on 4nm tech node.
• Integrate IP into the networking subsystem and document work.

Skills

SystemVerilog

Verilog

VHDL

Logic synthesis

EDA tools

Python

Tcl

Shell

C/C++

Networking protocols

AMBA

Job description

Kalray is offering an internship in Montbonnot (France) with the hardware digital design team. You will contribute to the development of DSP IPs and DPUs for AI and HPC data centers, from microarchitecture to physical synthesis, on a cutting-edge 4nm process.

You will work on RTL design (SystemVerilog/Verilog/VHDL), timing analysis, and integration into networking subsystems, gaining hands-on experience across the full design cycle in an agile, collaborative environment.