Analog Layout Engineers

Chipright; France; Sur place; EUR 90 000 - 120 000; Plein temps

Résumé du poste

Chipright seeks highly motivated Analog Layout Designers with high speed experience to work with our customer. The role involves designing analog layouts for high-performance blocks, debugging LVS/DRC issues, and collaborating with circuit designers to implement requested layouts.

Candidates should have a Bachelor’s degree in Electronics and 5–10 years of analog layout experience, with proficiency in Cadence Virtuoso and strong knowledge of electromigration, latch-up, and ESD considerations in

Qualifications

• Bachelor degree in Electronics or equivalent.
• 5–10 years of analog layout experience.
• Experience with high-speed analog blocks (ADC/DAC) is essential.
• Proficient analog layout skills; resolve electromigration, latch-up, ESD in sub-micron tech.
• GF 40nm CMOS or below experience.
• Ability to debug LVS/DRC errors independently.
• Ability to build electrical test bench and run electrical simulations is a plus.

Responsabilités

• Design analog layouts for high-speed blocks.
• Debug LVS/DRC errors and ensure layout correctness.
• Collaborate with circuit designers to meet requirements.
• Build/test benches and perform electrical simulations is a plus.

Connaissances

Analog Layout

High-speed design

Cadence Virtuoso

LVS/DRC debugging

Device matching

EM/EM

Power distribution

ESD

Formation

Bachelor's degree in Electronics

Outils

Cadence Virtuoso

Description du poste

Chipright seeks highly motivated and experienced Analog Layout Designers with high speedExperienceto work with our customer.This is a fantastic opportunity for talented engineers to work within a team of highly experienced engineers.Analog Layout EngineerExperience and Qualifications

• Must hold a Bachelor Degree in Electronics or equivalent.
• Minimum 5-10 years’ experience in Analog Layout Design.
• Experience working on high performance/ high speed Analog blocks (ADC/ DAC among others) is essential.
• Important to have proficient Analog Layout design skills and capability of solving device matching, electromigration, power distribution, latch-up and ESD in deep sub-micron technologies
• Relevant experience working on GF 40nm CMOS or below.
• Ability to debug and resolve LVS/DRC errors independently
• Ability to build electrical test bench and run electrical simulation is a plus
• Previous experience using cadence virtuoso tools.
• Good communication skills required and ability to interact withcircuit designers to understand their requirements and implement the requested layout.
• Possess necessary skill set to complete any assigned layout task with minimal supervision.

Senior Analog & AMS Recruitment Specialist