Freelance Analog IC Layout Engineer

XDigit; Grenoble; Sur place; EUR 68 880 - 110 208; Temps partiel

Résumé du poste

XDigit is building a team of freelancers for advanced full-custom analog layout projects in Grenoble, France. Remote work is possible with occasional on-site presence.

We seek strong hands-on expertise in the full-custom layout flow and physical sign-off, focusing on physical verification and advanced CMOS nodes below 28nm.

Key deliverables include block layout execution, DRC support, and final sign-off readiness, among others.

Qualifications

• Strong hands-on expertise in full-custom layout flow and physical sign-off.
• Experience with physical verification: DRC, LVS.
• Expertise in advanced CMOS nodes (below 28nm).

Responsabilités

• Execute block layout and hierarchical assembly.
• Support DRC and LVS closure.
• Manage PEX extraction and review.

Connaissances

Silicon-ready mindset

Strong methodology for matching

Complex hierarchical TOP integration

Clear communication

Description du poste

We are building our freelancer bench for upcoming advanced full-custom analog layout projects. Location: Grenoble, France. Remote is possible with occasional on-site presence when needed.

• Silicon-ready mindset and clean verification closure
• Strong methodology for matching and parasitic awareness
• Ability to handle complex hierarchical TOP integration
• Clear communication and milestone-driven delivery

Technical Requirements

We are looking for strong hands-on expertise in the full-custom layout flow and physical sign-off.

• Physical verification: DRC, LVS
• Parasitic extraction (PEX), sign-off oriented
• Advanced CMOS nodes (typically below 28nm)
• Analog layout best practices: matching, symmetry, shielding, guard rings
• Awareness of variations, coupling effects, and IR-drop considerations
• Full-custom physical verification and closure methodology
• TOP-level integration and complex hierarchical interconnect management

Typical Deliverables

The scope depends on the project phase. Common deliverables include:

• Block layout execution
• Hierarchical assembly
• DRC closure support
• LVS closure support
• PEX extraction and review
• Coupling and noise mitigation
• Power routing and IR-drop awareness
• Final physical sign-off readiness

Nice to have

• Experience across multiple advanced nodes
• Mixed-signal blocks (ADC, PLL, LDO, sensor front-ends)
• Comfortable in reviews and cross-team coordination