Advanced Packaging & Power Delivery Senior Engineer

Axelera AI; Paris; Hybride; EUR 70 000 - 95 000; Plein temps

Avantages offerts par ce poste

Attractive compensation package

Pension plan

Employee insurances

Company shares option

Flexible working arrangements

Résumé du poste

Axelera AI is looking for a Senior Advanced Packaging & Power Delivery Engineer to influence the silicon architecture of AI accelerators. You will manage power delivery design and lead packaging decisions for innovative systems.

Working within a dynamic R&D team, you will bridge analog design and packaging, ensuring the successful delivery of next-generation chips. Candidates should possess significant experience in semiconductor design and effective stakeholder communication skills.

Qualifications

• 7+ years of experience in power delivery or advanced packaging design.
• Expertise in on-die power grid design and package/PCB PDN analysis.
• Hands-on experience with 2.5D and/or 3D IC packaging technologies.

Responsabilités

• Own power-delivery design from on-die grids to PCB PDN.
• Lead advanced packaging architecture for multi-chiplet integration.
• Collaborate with teams to align power delivery solutions with product requirements.

Connaissances

Power delivery design

Advanced packaging technologies

Cross-functional communication

EDA tools for power integrity

Thermal modeling

Formation

Bachelor's or Master's degree in Electrical Engineering

PhD in a related field

Outils

EDA tools for PDN simulation

Power integrity software

Description du poste

Position Overview

As a Senior Advanced Packaging & Power Delivery Engineer at Axelera AI, you will play a pivotal role in shaping the silicon and packaging architecture of next‑generation AI accelerators. You will own power‑delivery design across the full stack – from on‑die power grids to package and PCB PDN – and bring deep expertise in advanced packaging technologies to help us scale from today’s products to tomorrow’s multi‑chiplet, 3D‑integrated systems.

Working within our R&D Custom Design team and collaborating closely with Silicon Engineering and AI Integrated Systems, you will be at the intersection of analog design, packaging innovation, and product delivery – with real ownership and direct impact on the chips we ship.

Key Responsibilities

• Own power‑delivery design end to end, from on‑die power grids to package and PCB PDN design and analysis.
• Lead advanced packaging architecture decisions for 2.5D/3D stacking, multi‑chiplet integration, and interposer/substrate co‑design.
• Perform SI/PI verification and sign‑off across the full stack, ensuring power integrity and signal integrity targets are met.
• Collaborate with the AIIS and Silicon Engineering teams to align power delivery and packaging solutions with product and silicon requirements.
• Support thermal and integration reviews for current and future products.
• Develop and maintain power‑delivery methodology, flows, and design guidelines within the Custom Design toolchain.
• Identify and mitigate single‑point‑of‑failure risks in SI/PI workstreams; mentor and grow the team's packaging expertise.
• Engage with external partners, substrate/interposer vendors, and OSAT houses to co‑develop advanced packaging solutions.

Qualifications

Required

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field; PhD is a plus.
• 7+ years of experience in power delivery and/or advanced packaging design in a semiconductor or deep‑tech environment.
• Demonstrated expertise in on‑die power grid design and package/PCB PDN analysis.
• Hands‑on experience with 2.5D and/or 3D IC packaging technologies, multi‑chiplet integration, and interposer/substrate co‑design.
• Proficiency with industry‑standard EDA tools for power integrity, PDN simulation, and package design.
• Ability to work cross‑functionally and communicate complex technical trade‑offs to diverse stakeholder groups.
• Strong written and spoken English communication skills.

Nice to Have

• Experience with SI/PI verification and sign‑off methodologies.
• Familiarity with thermal modeling and co‑simulation for integrated packages.
• Exposure to AI accelerator or custom ASIC design flows.
• Experience collaborating with OSAT partners, substrate vendors, or research institutes (e.g., imec).
• Knowledge of advanced node custom and analog design practices.

Location

We offer a flexible working arrangement, with options to:

• Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you are already based in the vicinity.
• Work fully remotely from any European country (incl. the UK) you are already in.
• Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven).

Kindly note that priority will be given to candidates who are interested in being based in Belgium or Italy.

What We Offer

This is your chance to shape and be part of a dynamic, fast‑growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.

An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.

Equal Opportunity

At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.