Senior Digital ASIC Designer: From Concept to Production

Murata Group

Vantaa

Hybrid

EUR 65,000 - 95,000

Full time

14 days+

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Job summary

Murata Finland is seeking a Senior Digital Design Engineer in Vantaa, Finland for digital ASIC design from concept to production, with a hybrid work model allowing partial remote work. You will collaborate with design partners, Murata lead engineers, product managers and the design team throughout the development process.

We require 3+ years of digital design experience, proficiency in Verilog/VHDL RTL coding, and experience with design verification tools and the RTL-to-GDSII flow.

Qualifications

  • Degree in digital microelectronics or a related field
  • At least 3+ years of digital design experience
  • Proficient in Verilog or VHDL RTL coding
  • Experience with digital design verification tools
  • Understanding of RTL-to-GDSII flow
  • Proactive, systematic and careful approach
  • Fluent in English
  • Strong communication with partners and teams
  • Innovative mindset for international work environments

Responsibilities

  • Design digital ASICs from concept through mass production ramp-up
  • Collaborate with design partners, Murata lead engineers, product managers and the design team
  • Contribute across the development lifecycle, from specification to validation
  • Support integration, testing and qualification activities

Skills

Digital design
Verilog/VHDL
RTL coding
English fluency

Education

B.Sc./M.Sc./Ph.D. in digital microelectronics

Tools

Matlab
Simulink
Python

Job description

Murata Finland is seeking a Senior Digital Design Engineer in Vantaa, Finland for digital ASIC design from concept to production, with a hybrid work model allowing partial remote work. You will collaborate with design partners, Murata lead engineers, product managers and the design team throughout the development process.

We require 3+ years of digital design experience, proficiency in Verilog/VHDL RTL coding, and experience with design verification tools and the RTL-to-GDSII flow.

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