Design Verification Engineer

118-WW TMG MFG OPS; Oulu; On-site; EUR 55,000 - 75,000; Full time

Benefits offered by this job

CAP program

Professional training

Job summary

Texas Instruments in Oulu, Finland seeks a Design Verification Engineer to verify analog and mixed-signal ICs during the design phase. You will develop test benches, apply stimulus, and report results to the project team.

You will work under a senior DV engineer within a cross-functional team and participate in the CAP program to accelerate your growth and long-term success at TI.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field.
• Experience designing electronic circuits and simulating with SPICE or similar.
• Understanding of basic analog/digital circuits (comparators, amplifiers, transistors).
• Familiarity with Verilog or VHDL languages.
• Good spoken and written English communication.

Responsibilities

• Develop detailed verification plans with the design and system teams.
• Implement mixed-signal testbenches in Cadence Virtuoso and SystemVerilog.
• Implement automatic checks and measurements to verify DUT behavior.
• Run coverage regressions to meet defined coverage goals.
• Track verification status, issues and concerns and communicate them.
• Develop scripts to submit cases for regression analysis and improvements to DV tools.

Skills

Circuit design

SPICE simulation

Verilog/VHDL

English communication

Education

Bachelors degree

Masters degree

Tools

Cadence Virtuoso

SystemVerilog

Verilog-A/AMS

SPICE

Job description

Change the world. Love your job.

Texas Instruments is seeking a skilled, enthusiastic Design Verification Engineer for our design group in Oulu, Finland. In this role you will work on confirming the functionality and performance of analog and mixed signal integrated circuits during IC design phase. This work requires you to study the target specification for the device being developed. You will then develop simulation test benches and automated checkers to verify design implementation and confirm top level functionality. Based on the simulations you have generated and completed, results will be reported out to the project team. In this role you will be interacting in a cross functional team to ensure bugs found are driven to complete closure. You will be working under the supervision of a senior DV engineer and in collaboration with the rest of the development team in an environment that will foster the growth of your professional experience and skills.

In your first year with TI, you will participate in the Career Accelerator Program (CAP), which provides professional and technical training and resources to accelerate your ramp into TI and set you up for long-term career success. Within this program, we also offer function-specific technical training and on-the-job learning opportunities that will encourage you to solve problems through a variety of hands-on, meaningful experiences from your very first day on the job.

As a Design Verification Engineer in the business, you will be responsible for:

• Developing detailed verification plans while working closely with the design and system team to ensure first pass silicon success
• Implementing mixed-signal testbenches in Cadence Virtuoso and SystemVerilog to apply stimulus and checks
• Implementing automatic checks and measurements to verify DUT behavior and populate a Spec Compliance Matrix (SCM)
• Running coverage regressions to meet the defined coverage goals
• Tracking and communicating verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

As part of your job, you will also get exposure to other roles such as: Digital Design& Analog Design through formal learning, projects and on-the-job development experiences that will help you broaden your knowledge and accelerate your growth and success at TI.

Put your talent to work with us as a Design Verification Engineer !

Minimum requirements

• Bachelors degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering or related field
• Some experience in designing electronic circuits and simulating them using SPICE or similar circuit simulators
• Understanding of basic electrical circuits like comparators, amplifiers, transistors and passive components
• Familiarity with Verilog or VHDL languages
• Good spoken and written communcations skills in English

Preferred qualifications:

• Masters degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering or related field
• Basic software skills in C/C++/Python or similar programming languages
• Understanding of power management functions like switching regulators and LDOs, as well as other analog functions like ADCs, DACs and so on
• Knowledge and experience in digital circuit design and implementation
• Creating behavioral models of analog circuits for example with SystemVerilog, Verilog-A or Verilog-AMS etc.
• Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
• Ability to quickly ramp on new systems and processes
• Demonstrated strong interpersonal, analytical and problem-solving skills
• Ability to work in teams and collaborate effectively with people in different functions
• Ability to take the initiative and drive for results
• Strong time management skills that enable on-time project delivery