Lead Design Engineer

Cadence Design Systems; Hämeenlinnan seutukunta; On-site; EUR 16,380 - 21,840; Full time

Job summary

Cadence Design Systems in multiple India locations seeks senior engineers for Xtensa processor RTL design and verification roles. You will implement cores and subsystems, run simulations, and partner with verification teams to meet timing, area, and power goals while mentoring junior engineers.

Requirements include 4+ years in design or verification, strong C/assembly and Verilog/SystemVerilog skills, and a solid background in digital design fundamentals.

Qualifications

• BS/MS in EE/Computer Engineering or similar field.
• Deep understanding of digital design and verification fundamentals.
• Experience as part of a team or mentoring junior engineers.
• Proficiency with Verilog/SystemVerilog and EDA tools.
• Experience in test plans, diagnostics, and coverage analysis.

Responsibilities

• RTL implementation of microprocessor cores and subsystems in Verilog.
• Simulate, debug, synthesize, place & route for timing and area goals.
• Develop test plans, write diagnostics, and analyze coverage.
• Collaborate with Design Verification and EDA teams.
• Assist with debugging and improve overall verification flow.

Skills

Team collaboration

Mentoring junior engineers

Strong communication

Analytical thinking

Problem solving

Education

BS/MS in EE/Computer Engineering

Tools

Verilog

SystemVerilog

EDA tools

UVM

Scripting (Python/Perl/Tcl)

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Tensilica CPU/DSP Processor Team is hiring senior engineers to join our R&D teams in Pune, Bangalore and Noida. This is an amazing opportunity to work in an impactful job at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great Processor team where you can make an impact that is visible.

Lead Engineer positions are for one of the two roles:

• Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
• Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

Required Skills and Experience

• 4+ years of Design or Design Verification experience
• BS/MS in EE/Computer Engineering or a similar major.
• Deep understanding of Digital Design and/or Design Verification fundamentals
• Experience in working as part of a team, or guiding/mentoring junior engineers
• Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
• Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
• Good working knowledge of scripting languages like Python, Perl, Tcl, Unix shell or similar languages
• Knowledge of technical safety concepts and requirement specifications according to ISO 26262
• Proficient with C language and assembly language
• Excellent written and oral communication skills necessary
• Exposure to debugging netlist/gate level simulation.
• General understanding of embedded SW.

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