Senior RTL/ASIC Engineer for High-Value SoC Design

Oesía Group; Rivas-Vaciamadrid; On-site; EUR 70,000 - 100,000; Full time

Job summary

Grupo Oesía in Madrid is seeking an experienced ASIC digital design engineer to join a multidisciplinary team. You will design, develop and integrate high-value SoC solutions, contributing from RTL coding to verification and collaboration with multiple disciplines.

The role emphasizes Verilog/SystemVerilog, RTL design, UVM verification, and collaboration across design, verification and physical implementation teams, with opportunities to influence architecture and silicon validation in strategic

Job description

Grupo Oesía in Madrid is seeking an experienced ASIC digital design engineer to join a multidisciplinary team. You will design, develop and integrate high-value SoC solutions, contributing from RTL coding to verification and collaboration with multiple disciplines.

The role emphasizes Verilog/SystemVerilog, RTL design, UVM verification, and collaboration across design, verification and physical implementation teams, with opportunities to influence architecture and silicon validation in strategic