RISC‑V Safety & Fault‑Tolerance Researcher

UNIVERSIDAD POLITECNICA DE MADRID; España; On-site; EUR 23,000 - 29,000; Full time

Job summary

UNIVERSIDAD POLITÉCNICA DE MADRID invites applications for a First Stage Researcher (R1) in the Engineering department. The role focuses on fault tolerance and safety mechanisms for RISC-V, with emphasis on safety islands, real-time concepts, and physical design for RISC-V cores with safety-critical requirements.

The successful candidate will hold a Master Degree in a related field, have expertise in HDL, C/C++, and RISC-V, and contribute to international projects in Madrid.

Qualifications

• Master degree in Electrical and Electronics Engineering, Telecommunication, Computer Engineering, or similar.
• Notion on RISC-V ISA and integration of accelerators; Embedded systems programming with C/C++.
• Desirable knowledge on fault-tolerance in electronic systems.

Responsibilities

• Research in fault tolerance and safety mechanisms for RISC-V.
• Research and develop concepts related to safety island and real time for RISC-V.
• Physical design for RISC-V cores with safety-critical requirements.

Skills

HDL Design

Embedded C/C++

RISC-V ISA knowledge

Education

Master's degree

Job description

UNIVERSIDAD POLITÉCNICA DE MADRID invites applications for a First Stage Researcher (R1) in the Engineering department. The role focuses on fault tolerance and safety mechanisms for RISC-V, with emphasis on safety islands, real-time concepts, and physical design for RISC-V cores with safety-critical requirements.

The successful candidate will hold a Master Degree in a related field, have expertise in HDL, C/C++, and RISC-V, and contribute to international projects in Madrid.