HRS2026/458 TFM on Advanced Circuits based on CMOS technology

UNIVERSIDAD POLITECNICA DE MADRID; España; On-site; EUR 20,000 - 28,000; Part time

Job summary

UNIVERSIDAD POLITÉCNICA DE MADRID seeks a First Stage Researcher (R1) for the IPTC project focusing on CMOS circuit design. The role covers design, validation, verification and testing of circuits, with potential to use the work for a Master thesis.

Applicants should be pursuing a master's degree in Electrical/Electronic Engineering or related fields, with excellent English and Spanish proficiency. The position is part-time (16 h/week), starting 30 Oct 2026 in Madrid, Spain.

Qualifications

• Background on design of CMOS circuits.
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Responsibilities

• Background on design of CMOS circuits.

Skills

CMOS circuit design

HDL design (Verilog/VHDL)

Computer architectures

Education

Bachelor Degree or equivalent (Electrical/Electronic Engineering)

Bachelor Degree or equivalent (Computer science)

Tools

Cadence

Synopsys

Job description

Organisation/Company UNIVERSIDAD POLITECNICA DE MADRID Department HRS4R Research Field Engineering >> Electronic engineering Researcher Profile First Stage Researcher (R1) Positions Bachelor Positions Application Deadline 16 Nov 2026 - 23:00 (Europe/Madrid) Country Spain Type of Contract Temporary Job Status Part-time Hours Per Week 16 Offer Starting Date 30 Oct 2026 Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research Infrastructure? No

Offer Description

• CMOS circuit design.


• Validation, verification and testing of circuits.

Requirements

Research Field Engineering Education Level Bachelor Degree or equivalent

Research Field Computer science Education Level Bachelor Degree or equivalent

Skills/Qualifications

Master's degree students in Electrical and Electronic Engineering, Telecommunications, or similar subjects.

Specific Requirements

• Background on design of CMOS circuits.


• Valuable Knowledge of comercial design tools like Cadence / Synopsys.


• Competence in computer architectures and digital system design with HDLs (Verilog or VHDL).

Currently, pursuing a master's degree with specific content on electronic design, the work can be used as Master thesis at the end of the 2026-2027 academic year.

Languages ENGLISH Level Excellent

Languages SPANISH Level Excellent

Research Field Other Years of Research Experience 1 - 4

Additional Information

The contracted researcher will participate in a joint program with INDRA, an international Spanish-based company, within the project "Chair UPM-INDRA in microelectronics".

Selection process

• Academic records at bachelor's level.


• Previous experience in the design of electronic circuits.


• Level of compliance with the specific requirements.

Work Location(s)

Number of offers available 1 Company/Institute Information Processing and Telecommunication Center (IPTC) Country Spain State/Province Madrid City Madrid Postal Code 28040 Street Avenida Complutense, 30 Geofield