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UNIVERSIDAD POLITECNICA DE MADRID invites applications for a First Stage Researcher (R1) in the Engineering field. The project focuses on fault-tolerant and real-time concepts for RISC-V, including safety islands and physical design for safety-critical cores.
The ideal candidate holds a Master’s degree in Electrical/Electronics Engineering or Computer Science and demonstrates proficiency in Verilog/VHDL, RISC-V, and C/C++.
Organisation/Company UNIVERSIDAD POLITECNICA DE MADRID Department HRS4R Research Field Engineering » Electronic engineering Researcher Profile First Stage Researcher (R1) Positions Master Positions Application Deadline 13 Nov 2026 - 23:00 (Europe/Madrid) Country Spain Type of Contract Permanent Job Status Full-time Hours Per Week 37,5 Offer Starting Date 29 Oct 2026 Is the job funded through the EU Research Framework Programme? Horizon Europe Is the Job related to staff position within a Research Infrastructure? No
Research Field Engineering Education Level Master Degree or equivalent
Research Field Computer science Education Level Master Degree or equivalent
Master degree on Electrical and Electronics Engineering, Telecommunication, Computer Engineering, Computer Science, or similar. Exceptional candidates who have completed a bachelor passed all master's subjects, and are only pending the defense of their master's thesis will also be considered.
Languages ENGLISH Level Excellent
Languages SPANISH Level Excellent
Research Field Engineering » Electronic engineering Years of Research Experience 1 - 4
The contract includes a gross salary of 25933,05 €, and full social benefits in Spain. The salary level is competitive for the current situation in Madrid. Conference, summer school and workshop registration fees will be also covered
Number of offers available 1 Company/Institute Centro de Electrónica Industrial y Sistemas Multimodales (CEIMM), Sede ETSII Country Spain State/Province Madrid City Madrid Postal Code 28008 Street C/ José Gutierrez Abascal, 2 Geofield