DDR Design Engineer

Hireroo Ltd; Barcelona; Híbrido; EUR 90.000 - 130.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible working hours

Hybrid model

Relocation bonus

Private medical insurance

Language classes

Visa support

Descripción de la vacante

Hireroo Ltd is seeking a Senior DDR Design Engineer in Barcelona to design, develop and integrate high performance memory subsystem solutions for advanced semiconductor products. You will work with architecture, RTL, verification and implementation teams across memory controller design, interface integration, timing and validation.

The role requires ownership of memory subsystem development and the ability to drive designs from architecture through tape-out, with a hybrid Barcelona location and

Formación

• 8+ years of relevant industry experience.
• Strong DDR or HBM memory experience.
• Proven memory controller design or integration experience.
• Strong knowledge of AXI protocol.
• RTL design using Verilog or VHDL.
• Experience with timing and timing constraints.
• Block level testing and validation.
• Understanding of SoC memory subsystem integration.
• Strong debugging and problem solving skills.
• Ability to work across architecture, RTL and verification teams.

Responsabilidades

• Design and integrate DDR or HBM memory subsystems
• Develop and integrate memory controllers within SoC environments
• Implement and review RTL using Verilog or VHDL
• Work with AXI based interfaces and system integration
• Translate architecture requirements into robust memory subsystem designs
• Apply timing constraints and support timing analysis and closure
• Perform block level testing and validation
• Debug memory subsystem and interface issues
• Collaborate with architecture, RTL and verification teams
• Support integration through implementation and tape out
• Contribute to design reviews and technical decisions

Conocimientos

DDR/HBM memory

Memory controller design

AXI protocol

Verilog/VHDL RTL

Timing analysis

SoC integration

Debugging skills

Cross-team collaboration

Educación

Master or PhD

Herramientas

Git

SVN

Python

Perl

Bash

Tcl

Descripción del empleo

Job Description

Our partner is looking for a Senior DDR Design Engineer to design, develop and integrate high performance memory subsystem solutions for advanced semiconductor products.

You will work closely with architecture, RTL, verification and implementation teams on memory controller design, interface integration, timing and validation. The role requires strong ownership of memory subsystem development and the ability to support designs from architecture through implementation and tape out.

Location: Barcelona, Spain, Hybrid
Level: Senior

Responsibilities

• Design and integrate DDR or HBM memory subsystems
• Develop and integrate memory controllers within SoC environments
• Implement and review RTL using Verilog or VHDL
• Work with AXI based interfaces and system integration
• Translate architecture requirements into robust memory subsystem designs
• Apply timing constraints and support timing analysis and closure
• Perform block level testing and validation
• Debug memory subsystem and interface issues
• Collaborate with architecture, RTL and verification teams
• Support integration through implementation and tape out
• Contribute to design reviews and technical decisions

Requirements

• 8+ years of relevant industry experience
• Strong DDR or HBM memory experience
• Proven memory controller design or integration experience
• Strong knowledge of AXI protocol
• RTL design using Verilog or VHDL
• Experience with timing and timing constraints
• Block level testing and validation
• Understanding of SoC memory subsystem integration
• Strong debugging and problem solving skills
• Ability to work across architecture, RTL and verification teams

Optional / Desired

• RISC V architecture experience
• Master or PhD
• Python, Perl, Bash or Tcl
• Git or SVN
• Participation in 2 successful tape outs
• Experience with complex SoC memory subsystems
• Experience supporting timing closure and integration
• Broader knowledge of memory architecture and system performance

What’s in it for you?

• Flexible working hours
• Hybrid model, 4 days office, 1 day from home
• 1 week per year working from anywhere
• 25 days annual leave plus December 24 and 31
• Monthly food allowance
• Private medical insurance
• Relocation bonus
• Housing search support
• Visa support if required
• Family relocation support
• Virtual shares
• Language classes
• Tax incentive, subject to eligibility