Senior Digital Design Engineer

Beagle; Barcelona; On-site; EUR 90,000 - 120,000; Full time

Job summary

A leading semiconductor company in Barcelona is seeking a Senior Digital Design Engineer to design and develop high-performance memory subsystems for modern SoCs. The ideal candidate will have over 8 years of industrial experience and expertise in DDR or HBM memories. This full-time role involves collaborating closely with engineering teams to create efficient memory architectures.

Qualifications

• 8+ years of industrial experience in digital design.
• Proven experience designing or integrating memory controllers.
• Knowledge of coherency concepts and protocols.
• Proven experience designing or integrating memory controllers.
• Hands-on experience with AXI protocol.
• Proficiency in RTL design (Verilog or VHDL).
• Experience with timing constraints and basic block-level testing.
• Master’s degree or PhD.
• Experience with version control (git, svn).
• Knowledge of coherency concepts and protocols.

Responsibilities

• Define, design, and implement memory controllers and subsystems (DDR, HBM).
• Develop and verify RTL (Verilog or VHDL) for memory blocks.
• Work with timing constraints and perform block-level testing.
• Integrate memory IPs into SoC environments.
• Collaborate with cross-functional teams.

Skills

Digital design experience

DDR or HBM knowledge

Memory controller design

RTL design (Verilog or VHDL)

Timing constraints experience

Version control (git, svn)

Testing/Verification

Coherency concepts

Git/SVN

Education

Master’s degree or PhD

Tools

Git

SVN

Job description

Connecting Ambitious Tech Companies with Exceptional Talent | Partner at Beagle | Semiconductor & Embedded Focus

LOCATION: Barcelona, Spain

SALARY: Negotiable

DURATION: Permanent

We are looking for a Senior Digital Design Engineer to design and develop high-performance memory subsystems for modern SoCs. You will work within the Memory Design Team and collaborate closely with other engineers to create efficient and robust memory architectures.

Responsibilities:

• Define, design, and implement memory controllers and subsystems (DDR, HBM)
• Develop and verify RTL (Verilog or VHDL) for memory blocks
• Work with timing constraints and perform block-level testing
• Integrate memory IPs into SoC environments
• Collaborate with cross‑functional teams to ensure coherency and high‑performance operation

Required:

• 8+ years of industrial experience in digital design
• Strong knowledge of DDR or HBM memories
• Proven experience designing or integrating memory controllers
• Hands‑on experience with AXI protocol
• Proficiency in RTL design (Verilog or VHDL)
• Experience with timing constraints and basic block‑level testing
• Master’s degree or PhD
• Experience with version control (git, svn)
• Knowledge of coherency concepts and protocols

Seniority level

• Mid‑Senior level

Employment type

• Full‑time

Job function

• Engineering and Design
• Semiconductor Manufacturing, Appliances, Electrical, and Electronics Manufacturing, and Computers and Electronics Manufacturing

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