Digital Verification Engineer – Semiconductor (all gender)

ALTEN Germany; München; Vor Ort; EUR 65.000 - 85.000; Vollzeit

Benefits dieser Stelle

Flexible working hours

Mobile working options

Corporate benefits

Team events

Bike leasing

Green Mobility discounts

Zusammenfassung

A leading engineering service provider in Munich is seeking an engineer to verify mixed-signal designs using formal and functional methods. The ideal candidate will hold an engineering degree and possess programming skills in System Verilog while having experience in digital verification. Excellent communication skills in English are required. This position offers a permanent contract, flexible working hours, and various employee benefits, including career development options and a focus on work-life balance.

Qualifikationen

• Completed an engineering degree in electrical engineering, computer science, or similar.
• Experience in digital functional verification and safety standards.
• Extensive programming skills in System Verilog and assertions.

Aufgaben

• Verify mixed-signal designs via formal and functional verification.
• Interpret product requirements to create verification specifications.
• Collaborate with engineers across multiple sites.

Kenntnisse

Digital functional verification

System Verilog

UVM methodology

Python scripting

English communication skills

Ausbildung

Engineering degree in electrical engineering or computer science

Jobbeschreibung

Overview

We are the designers of today for the world of tomorrow. As one of the world's leading engineering service providers, we at ALTEN are committed to positively shaping the future of our partners, the careers of our employees and the challenges facing our society and environment.

More than 50,000 employees in 30 countries are already working on innovative solutions in various engineering and IT sectors such as aerospace, renewable energy, medical technology, railway technology and automotive.

Job Description

YOU…

• verify mixed-signal designs on block and system level resting upon formal and functional verification
• interpret product requirements to create the verification concept and the product verification specification
• perform random-constraint testbenches according to the state of the art
• create assertions to prove the design using formal methods
• work in collaboration with lab and test engineers, designers, system architects, and verification engineers across multiple sites

Qualifications

• have completed engineering degree in electrical engineering, computer science or similar studies
• already have practical experience in the field of digital functional verification and common safety standards
• have extensive programming skills in coding in System Verilog and System Verilog assertions
• have good knowledge of UVM methodology, scripting languages like Python or Perl and ability to interpret RTL and Gatelevel code
• have good communication skills in English

We value diversity and therefore welcome all applications - regardless of gender, nationality, ethnic and social origin, religion/belief, disability, age and sexual orientation and identity. Severely disabled persons will be given preferential consideration if they are equally qualified.

Do you have any questions?

Then contact me: Özlem Mumin (Tel.: [phone])

Apply now

Or apply now using our online application form.

Additional Information

• Talent Management - we develop your career
• Work life balance - flexible working hours and mobile working possible
• Fit and relaxed – with EGYM Wellpass
• Enjoy biking – always on tour with bike leasing
• Green Mobility - with us you can travel at a reduced rate

...in addition we offer a permanent employment contract, corporate benefits and team events.