Sr. Engineer, Layout Design

SiTime; Berlin; Vor Ort; EUR 95.000 - 140.000; Vollzeit

Benefits dieser Stelle

Quarterly bonus

Equity grants

Zusammenfassung

SiTime is seeking a Sr. Layout Design Engineer in Berlin to lead chip-planning and block-level custom layouts for CMOS and BiCMOS circuits. You will coordinate with offshore layout teams, train junior engineers, and help develop standard methodologies across sites to achieve high layout quality.

The role requires remote interfacing with multiple design centers, proficiency in Cadence Virtuoso, and strong debugging of DRC/LVS/ERC. You will contribute to tape-out and process integration efforts.

Qualifikationen

• BA/BS Degree in Layout Design or related field, or equivalent experience.
• 10 years’ experience with layout design for analog and full-custom digital blocks.
• Experience with TSMC 180nm, 65nm, 22nm and UMC 55nm process technologies.
• Proficient in using layout editing tools in the Cadence Virtuoso design environment.
• Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre.

Aufgaben

• Lead top-level chip-planning and perform functional-block-level, block-level, sub-block, leaf cell, and standard cell custom layouts for CMOS and BiCMOS circuits.
• Perform schematic-driven layout and design constraints.
• Design die-area efficient layouts according to circuit designer requirements.
• Perform block or top-level layout designs.
• Perform floor-planning, powerline planning, shielding, and device-matching layout.
• Verify layouts. Pass DRC, LVS, and ERC checks.
• Contribute to various chip-level routing and layout needs.
• Perform chip-level integration, verifications, and tape-out.
• Train junior layout engineers and offshore layout contractors.
• Contribute to developing common best practices and workflow across all sites.

Kenntnisse

Layout design expertise

Analog and digital block design

Cadence Virtuoso

DRC/LVS/ERC debugging

Team collaboration

Ausbildung

BA/BS Degree in Layout Design or related field

Tools

Cadence Virtuoso

Mentor Calibre

Cadence PVS

Jobbeschreibung

About SiTime

SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com.

Job Summary

The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The engineer will review and coordinate work performed by offshore layout designers, train junior layout engineers and offshore contractors, contribute to developing standard layout methodologies across sites, and build processes and procedures to achieve high layout quality.

Responsibilities

• Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones.
• Lead top-level chip-planning and perform functional-block-level, block-level, sub-block, leaf cell, and standard cell custom layouts for CMOS and BiCMOS circuits.
• Perform schematic-driven layout and design constraints.
• Design die-area efficient layouts according to circuit designer requirements.
• Perform block or top-level layout designs.
• Perform floor-planning, powerline planning, shielding, and device-matching layout.
• Verify layouts. Pass DRC, LVS, and ERC checks.
• Contribute to various chip-level routing and layout needs.
• Perform chip-level integration, verifications, and tape-out.
• Support other projects as needed by management.
• Train junior layout engineers and offshore layout contractors.
• Contribute to developing common best practices and workflow across all sites.
• Build processes and procedures to achieve high layout quality.

Qualifications & Requirements

• BA/BS Degree in Layout Design or related field, or equivalent experience.
• 10 years’ experience with layout design for analog and full-custom digital blocks.
• Experience with TSMC 180nm, 65nm, 22nm and UMC 55nm process technologies.
• Proficient in using layout editing tools in the Cadence Virtuoso design environment.
• Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre.
• Conceptual understanding of layout topics such as parasitic effects, matching, crosstalk, transistor layout dependent effects, latch‑up, IR drop, electromigration (EM), and deep N‑well and N‑T isolation.
• Strong capability of solving device matching, EM, signal integrity and power distribution problems while meeting area constraints.
• Experience in chip-level floor planning and analog block integration.
• Experience with chip-level integration, verifications, and tape-out.
• Ability to use productivity-enhancing tools and design scripts to further automate tasks.
• Must be able to lift, push, and pull up to 5 lbs.

Desired Characteristics & Attributes

• Attention to detail, organized, accurate, and able to produce efficient layout techniques.
• Has a good track record of on-time work delivery.
• Self‑motivated, team player with good communication skills.
• Works well with others in a fast‑paced collaborative team environment.

Compensation Range

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals, and equity grants are also provided.

Equal Opportunity Statement

SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, marital status or other characteristics protected by law.

Learn More about SiTime

• Innovation on Top – Philosophies of Innovation with Rajesh Vashist
• Fabrication Knowledge – An Interview with Rajesh Vashist
• SiTime Corporation – YouTube