Engineer II, Analog Mixed-Signal Design

SiTime; Berlin; On-site; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Quarterly bonus

Equity grants

Competitive compensation package

Job summary

SiTime is seeking an Analog Mixed‑Signal Designer II to join our team in Berlin. You will contribute to precision timing circuits based on SiTime's MEMS technology for high‑performance networking and mobile applications.

You will design, verify, and optimize analog blocks, collaborate with layout and product teams, and support chip bring‑up and characterization to ensure blocks meet stringent specifications.

Qualifications

• Bachelor’s or higher degree in a relevant field with strong academic record.
• Experience in Analog/Mixed-Signal design and verification is required.
• Knowledge of industry standard EDA tools and design flows is desirable.

Responsibilities

• Design Analog and Mixed‑Signal circuits to meet architectural specs.
• Contribute to chip architecture and integration efforts.
• Perform schematic and post‑layout verification, including DFT/DFM considerations.

Skills

Team collaboration

Attention to detail

Strong communication

Education

MS in Electrical Engineering

PhD preferred

Tools

Matlab

VerilogA

Oceanscript

Job description

Job Summary

The Analog Mixed Signal Designer II contributes to building precision timing circuits, leveraging SiTime’s industry‑leading MEMS technology, that span high‑performance Networking and Communications Infrastructure market application requirements and ultra‑low power Mobile platforms including wearable devices.

Responsibilities

• Design Analog and Mixed‑Signal circuits, meeting their architectural requirements and technical specifications
• Contribute to the architectural definition of the design, and also to chip integration
• Perform the necessary calculations, design and verification simulations to ensure building blocks meet specifications, at the schematic level and after post‑layout extraction, while fully provisioning for DFT and DFM
• Work closely with Layout Designers to ensure the layout is completed properly, using all best known methods
• Document assigned blocks, and hold preliminary and final design reviews
• Actively participate in the chip bring‑up, evaluation and characterization, with emphasis on owned blocks
• Address questions and issues related to blocks raised by cross‑functional personnel, such as Product, Characterization, Test, or Application Engineers
• Drive other projects as needed by management or as business needs change

Qualifications & Requirements

• MS Degree in Electrical Engineering with minimum 3 years of related experience, or PhD preferred with no minimum work experience
• Design expertise in one of the following areas:
  • PLLs: Sigma‑Delta and LC
  • ADCs: preferably > 14 ENOB
  • Temperature Sensor
  • Quartz or MEMS Oscillator
  • Sub‑threshold circuits
  • Low‑noise regulator and Band gaps
• Knowledge of programming languages: Matlab, VerilogA, Oceanscript
• Ability to oversee circuit layout for critical blocks
• Ability to perform noise analysis

Desired Characteristics & Attributes

• Excellent written and verbal communication skills required
• Ability to work well with others in a collaborative, fast‑paced team environment

Compensation Range

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

SiTime is an Equal Opportunity Employer. We treat each person fairly and do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law.