Sr. DDR PHY Design Engineer - Munich, Germany

microTECH Global Ltd; Bayern; Vor Ort; EUR 60.000 - 100.000; Vollzeit

Zusammenfassung

An innovative company is seeking a skilled DDR PHY Design Engineer to lead the development of high-performance DDR interfaces. In this pivotal role, you will engage in all phases of PHY design, from architecture to final GDSII delivery. Your expertise will drive the creation of top-tier PHY solutions, collaborating closely with cross-functional teams to ensure successful implementation. This role offers a unique opportunity to influence the future of cutting-edge technology in a dynamic environment. If you are passionate about PHY design and eager to make a significant impact, this position is perfect for you.

Qualifikationen

• 5+ years of experience in DDR PHY design for high-performance SoCs.
• Solid understanding of PHY construction, integration, and physical design.

Aufgaben

• Participate in architecture development of next-gen DDR PHY.
• Design DDR PHY from architecture to micro-architecture.
• Define specifications and verification processes for DDR PHY design.

Kenntnisse

DDR PHY Design

RTL Writing

Verification Tools

SoC Design

HDL Languages (Verilog)

Scripting Languages (Perl, Tcl)

Design Methodologies

Tools

RTL Design Tools

Synthesis Tools

Extraction Tools

STA Methodologies

Jobbeschreibung

In this role, you will be at the center of a PHY design effort interfacing with architecture, CAD, timing, and PD design teams, with a critical impact on delivering best-in-class PHY designs. You will be responsible for designing top-tier PHY solutions.

Description :

Core Responsibilities :

As a DDR PHY Design engineer, you will be involved in all phases of PHY design for high-performance DDR interfaces, from architecture and RTL to the delivery of final GDSII files.

Your responsibilities include, but are not limited to :

1. Participate in the architecture development of next-generation DDR PHY.
2. Design DDR PHY from architecture to micro-architecture.
3. Implement RTL for the micro-architecture.
4. Define specifications, testing, and verification processes for DDR PHY design.
5. Collaborate with CAD and PD teams to implement RTL designs into GDSII.
6. Run various design verification flows at the PHY level and provide guidance to other designers.
7. Establish CAD and design methodologies for correct-by-construction designs.
8. Assist in developing flows for PHY integration.

Qualifications :

The ideal candidate will have 5+ years of DDR PHY design experience in high-performance, low-power SoC designs.

1. Knowledge of industry standards and practices in PHY design, including RTL writing and verification tools.
2. Experience in developing and implementing DDR PHY.
3. Solid understanding of all aspects of PHY construction, integration, and physical design.
4. Knowledge of basic SoC architecture and HDL languages like Verilog for timing fixes.
5. Knowledge of circuit design and transistor operation is a plus.
6. Proficiency with industry-standard RTL design and synthesis tools.
7. Solid understanding of scripting languages such as Perl or Tcl.
8. Working knowledge of extraction and STA methodologies and tools.
9. Good understanding of design methodologies to debug PHY-level issues.