Senior Static Timing Analysis (STA) Engineer (f/m/div)

ZipRecruiter; Dresden; Vor Ort; EUR 75.000 - 100.000; Vollzeit

Zusammenfassung

A leading company in semiconductor solutions is seeking a Senior Static Timing Analysis Engineer to drive innovations in timing sign-off. The role involves developing cutting-edge methods for timing analysis in advanced technologies, collaborating to ensure product performance, all while contributing to green energy solutions.

Qualifikationen

• Minimum 5 years of experience in timing analysis and verification or chip design.
• Experience with timing analysis methods and SPICE simulation.
• Fluent in English; knowledge of German is a plus.

Aufgaben

• Develop methods for timing sign-off processes for technologies from 5nm to 130nm.
• Evaluate and update timing sign-off guidelines.
• Analyze DSM effects relative to performance and power.

Kenntnisse

Static Timing Analysis

SPICE simulation

Programming in Perl

Programming in Python

Circuit design

English communication

German communication

Ausbildung

Technical degree in Electrical Engineering, Computer Science, Physics, or related

Jobbeschreibung

Job Description

Senior Static Timing Analysis (STA) Engineer (f/m/div) - Unlock the Secrets of Timing Sign-Off: Join Our Team of Experts! Are you ready to push the boundaries of digital timing sign-off? Do you have a passion for analyzing DSM effects and optimizing product performance?

We're looking for a talented professional to develop and implement cutting-edge methods for timing sign-off. If you're up for the challenge, apply now and take your skills to the next level!

In your new role, you will:

1. Develop and implement methods for timing sign-off process supporting technologies from 5nm to 130nm
2. Evaluate and update digital timing sign-off guidelines
3. Analyze DSM effects and their relevance for performance and power
4. Develop methods to predict, assess, and measure the performance of products
5. Assess and evaluate external foundry sign-off regulations
6. Investigate observed and described effects
7. Transfer dynamic effects into static analysis methods
8. Determine and fine-tune implementation and signoff guard bands for optimal design robustness

As a Senior Staff Engineer in Timing Signoff, you are committed to customer concerns and prioritize them highly. You set ambitious goals and can quickly establish successful cooperation.

You are best equipped for this role if you have:

• A technical degree in Electrical Engineering, Computer Science, Physics, or a similar qualification
• At least 5 years of experience in timing analysis and verification and/or digital chip design
• Experience in Static Timing Analysis and SPICE simulation
• Advanced programming skills in Perl/Python, preferably also in SQL
• A good understanding of hardware description and circuit design
• Background knowledge of uncertainties in chip design and timing verification
• Fluent communication skills in English; German is a plus

Contact: Carolina Moreira

More info on LinkedIn: #WeAreIn

About Infineon: As a global leader in semiconductor solutions for power systems and IoT, we enable innovations for green energy, mobility, and smart IoT. Join us to make life easier, safer, and greener.

Our organization, 'Design Enabling and Services' (DES), provides design environments to product development teams, supporting the entire value chain from system models to verified product layouts, ensuring high-quality manufacturing readiness.

We embrace diversity and are committed to equal opportunities. We look forward to your application, even if you do not meet all requirements. Please inform your recruiter of any specific considerations for your interview process. For more info about working at Infineon, click here.