Senior RTL Engineer, Interconnect Design

Openai; Deutschland; Vor Ort; EUR 70.000 - 100.000; Vollzeit

Zusammenfassung

OpenAI is seeking a highly experienced RTL engineer to lead the design of critical on-and off-chip interconnect components for their custom AI accelerator platform. This senior engineering role involves driving microarchitecture and RTL implementation, ensuring connection of high-bandwidth compute and memory systems.

As part of the Hardware team, you will oversee the entire design process from requirements to verification closure, contributing to the next-generation AI-native silicon.

Qualifikationen

• Extensive experience in RTL design, especially for AI systems.
• Ability to drive microarchitecture and RTL implementation.
• Experience with verification closure.

Aufgaben

• Own the design of on-and off-chip interconnect components.
• Drive microarchitecture and RTL implementation.
• Engage in performance analysis throughout the silicon lifecycle.

Kenntnisse

RTL design

Microarchitecture

On-chip communication

Performance analysis

Ausbildung

Degree in Electrical Engineering or related field

Jobbeschreibung

About the Team

OpenAI’s Hardware organization develops silicon and system‑level solutions designed for the unique demands of advanced AI workloads. The team is building next‑generation AI‑native silicon and infrastructure to support large‑scale training and inference systems. Within Hardware, the SoC design team works across architecture, RTL design, verification, physical design, performance, firmware, and systems engineering to deliver production‑quality silicon for OpenAI’s supercomputing infrastructure.

About the Role

We are looking for a highly experienced RTL engineer to own critical on‑and off‑chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on‑chip communication fabrics connecting high‑bandwidth compute, memory, and I/O subsystems as well as purpose‑built off‑chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands‑on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure.