Expert Hardware / RTL Engineer – SystemVerilog / Verilog

aitrainer; Deutschland; Vor Ort; EUR 130.040 - 224.615; Teilzeit

Zusammenfassung

aitrainer in Germany is looking for expert hardware engineers to evaluate advanced AI systems in engineering. The ideal candidate has 5+ years of RTL experience in SystemVerilog or Verilog, and familiarity with tools like Vivado and Docker.

This role involves evaluating technical tasks, reviewing complex code, and providing clear assessments. Compensation ranges from $110 to $190 per hour based on experience, with expected commitment between 20 to 40 hours per week.

Qualifikationen

• 5+ years of professional or research RTL experience in SystemVerilog or Verilog.
• Hands-on depth in RTL design, testbench/UVM verification, FPGA or ASIC work.
• Comfort working in Linux/Docker-based repo environments.

Aufgaben

• Apply your RTL expertise to evaluate technical tasks against standards.
• Review intricate code-level situations and provide structured assessments.
• Provide clear written rationales explaining your expert judgments.

Kenntnisse

SystemVerilog

RTL design

Verilog

EDA toolchains

Docker

Tools

Vivado

Quartus

Synopsys

Cadence

Jobbeschreibung

About the Opportunity

A leading AI research organization is evaluating how advanced AI systems perform in specialized engineering domains, and is seeking expert hardware engineers with deep, hands-on RTL experience in SystemVerilog and/or Verilog. You'll apply your expertise to assess complex, real-world technical scenarios — directly shaping how cutting-edge AI performs in hardware design. Single-language specialists are strongly encouraged to apply.

What You'll Do

• Apply your RTL expertise to evaluate technical tasks against real-world professional standards
• Review intricate code-level situations and provide precise, structured written assessments
• Work inside containerized repositories (Docker), running and interpreting programmatic and CI-style checks to judge whether an engineering environment is sound
• Provide clear written rationales explaining your expert judgments
• Complete well-defined, time-bounded tasks with explicit evaluation criteria

Who We're Looking For

• We value strong engineering fundamentals, fast ramp-up, and high ownership over single-language pedigree alone — but deep specialists are very welcome. The ideal candidate brings:
• 5+ years of professional or research RTL experience in SystemVerilog or Verilog
• Hands-on depth in RTL design, testbench/UVM verification, FPGA or ASIC work, and EDA toolchains (Vivado, Quartus, Synopsys, Cadence)
• Comfort working in Linux/Docker-based repo environments and reading automated/CI checks — or the ability to ramp on these fast
• Ability to articulate not just what code does but why it's correct or idiomatic, clearly in writing
• Welcomed: engineers from semiconductor, telecom, defense/aerospace, national-lab, or academic backgrounds; non-traditional digital footprints are fine — a GitHub profile is not required

Why This Work Matters

RTL design underpins the world's semiconductors yet remains among the least-represented domains in AI research. The expertise you bring is rare, and your assessments directly influence how AI systems learn to operate in it.

Engagement Details

• Compensation: $110–190/hour, based on depth and experience
• Expected commitment: 20–40 hrs/week
• Task flow is variable — work tends to arrive in waves, and there can be a lag between task batches. We're looking for people who stay flexible, including availability on weekends when needed, and who take ownership of keeping the project moving forward
• No proprietary tooling required — tasks are completable without employer-provided systems
• We consider all qualified applicants without regard to legally protected characteristics and provide reasonable accommodations upon request.