Senior Digital Design Engineer - (Visa Sponsorship Supported)

European Tech Recruit; Nordrhein-Westfalen; Vor Ort; EUR 60.000 - 90.000; Vollzeit

Zusammenfassung

A leading semiconductor company in Nordrhein-Westfalen is seeking a Digital Design Engineer. The role focuses on developing high-performance digital and mixed-signal ICs and requires expertise in RTL design. Ideal candidates will have a background in EDA tools and experience ranging from 3 to over 6 years in digital IC design. This position promises a dynamic work environment with opportunities for innovation in cutting-edge technology.

Qualifikationen

• Mid-Level: 3–5 years of relevant digital IC design experience.
• Senior-Level: 6+ years with ownership of IP/SoC blocks.
• Hands-on experience in physical implementation including floorplanning, P&R.

Aufgaben

• Design and develop RTL and micro-architecture for digital subsystems.
• Optimize backend flow including synthesis, floorplanning, and timing closure.
• Collaborate with physical design teams for seamless handoff.

Kenntnisse

RTL design using SystemVerilog / VHDL

Digital verification

Scripting (Python, Tcl)

Low-power design techniques

Attention to detail

Ausbildung

MS or PhD in Electrical Engineering

Tools

EDA tools from Cadence

EDA tools from Synopsys

EDA tools from Mentor

Jobbeschreibung

Digital Design Engineer

Join an award-winning semiconductor company specializing in innovative wide bandwidth transceivers, including patented microchips for ultrafast 5G-A and 6G wireless infrastructure.

About the Role

We seek Digital Design Engineers with expertise in frontend RTL design, backend physical implementation, or both. You will develop high-performance digital and mixed-signal ICs using advanced technology nodes such as 22FDX and other FinFET / FD-SOI processes.

Responsibilities

• Design and develop RTL and micro-architecture for digital subsystems (e.g., DSP blocks, control logic, interfaces).
• Optimize backend flow including synthesis, floorplanning, placement, routing, timing closure, and signoff (STA, LVS, DRC).
• Collaborate with physical design teams to ensure seamless handoff and alignment across digital and mixed-signal boundaries.
• Support integration of digital blocks with analog/mixed-signal systems.
• Create documentation, testbenches, and assist with post-silicon testing and debugging.

Your Profile

• Proficient in RTL design using SystemVerilog / VHDL, digital verification, and scripting (Python, Tcl, etc.).
• Experienced with EDA tools from Cadence, Synopsys, or Mentor for synthesis, STA, and backend implementation.
• Knowledge of low-power design techniques, clock domain crossing (CDC), and hierarchical SoC design.
• Hands-on experience in physical implementation including floorplanning, P&R, CTS, STA, DRC, LVS.
• Familiar with modern process nodes, especially 22FDX, 16/12nm FinFET, or similar, and mixed-signal integration, top-level assembly, and testability concepts (DFT is a plus).
• Strong problem-solving skills, attention to detail, and ability to work independently.

Qualifications

• Mid-Level: 3–5 years of relevant digital IC design experience.
• Senior-Level: 6+ years, with ownership of IP/SoC blocks or backend flows.
• MS or PhD in Electrical Engineering, Microelectronics, or related field.

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