Senior Digital Design Engineer

Intellectual Capital Resources Ltd; Baden-Württemberg; On-site; EUR 120,000 - 160,000; Full time

Job summary

Intellectual Capital Resources Ltd invites an experienced Senior Digital ASIC Design Engineer to join our hardware R&D team in Böblingen, Germany. You will own architecture and silicon for advanced mixed-signal ASICs, leading from concept through verification and final silicon.

The role requires 10+ years in digital ASIC/SoC design, expert RTL/Verilog skills, and a deep understanding of CMOS/mixed-signal processes. Relocation to Germany is welcomed for the right candidate.

Qualifications

• 10+ years of digital ASIC/SoC design experience.
• Expert-level RTL and Verilog skills.
• Strong understanding of the ASIC development lifecycle.
• Experience with mixed-signal ASICs and CMOS.
• Broad digital design expertise, not FPGA-focused.
• Degree in Electrical/Electronic Engineering or equivalent.

Responsibilities

• Lead digital ASIC/SoC design from concept and architecture through to silicon.
• Develop complex RTL/Verilog designs within mixed-signal ASICs.
• Drive architecture, design and chip-level verification.
• Collaborate with senior system, hardware and software engineers.
• Solve challenging technical problems across the full ASIC lifecycle.
• Mentor junior engineers and act as a technical authority.

Skills

RTL/Verilog

Digital ASIC design

CMOS tech

Technical communication

Education

Electrical/Electronic Engineering degree

Tools

Verilog HDL

Job description

Senior Digital ASIC Design Engineer - Mixed-Signal ASIC Böblingen, Germany | Senior/Expert Level

A global technology leader is looking for an Senior Digital ASIC Design Engineer to join a highly experienced hardware R&D team developing advanced semiconductor technology.

This is a rare opportunity to take real ownership of complex ASICs from architecture through to silicon, working on sophisticated mixed-signal devices used in next-generation semiconductor test systems.

The Role

• Lead digital ASIC/SoC design from concept and architecture through to silicon
• Develop complex RTL/Verilog designs within mixed-signal ASICs
• Drive architecture, design and chip-level verification
• Work closely with senior system, hardware and software engineers
• Solve challenging technical problems across the full ASIC lifecycle
• Mentor junior engineers and act as a technical authority within the team

What We’re Looking For

• 10+ years’ experience in digital ASIC/SoC design
• Expert-level RTL and Verilog skills
• Strong understanding of the ASIC development and silicon lifecycle
• Experience with mixed-signal ASICs and CMOS
• Broad digital design expertise, this is not an FPGA-focused role
• Strong technical communication and problem-solving skills
• Degree in Electrical/Electronic Engineering or equivalent

Why Consider It?

A chance to move beyond simply implementing designs and have genuine influence over architecture, technology and silicon.

You’ll be joining a technically strong team working on highly complex hardware where experienced engineers are trusted to make decisions, solve difficult problems and shape the next generation of semiconductor technology.

Böblingen, Germany. European candidates willing to relocate are welcome. Candidates already based in Germany are preferred.